Texas Instruments CC2650DK 사용자 설명서
UARTS Registers
19.7.1.4 FR Register (Offset = 18h) [reset = X]
FR is shown in
and described in
Flag Reads from this register return the UART flags.
Figure 19-7. FR Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
TXFE
RXFF
TXFF
RXFE
BUSY
RESERVED
CTS
R-1h
R-X
R-X
R-1h
R-X
R-X
R-0h
Table 19-7. FR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7
TXFE
R
1h
UART Transmit FIFO Empty: The meaning of this bit depends on the
state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the
transmit holding register is empty. - If the FIFO is enabled, this bit is
set when the transmit FIFO is empty. This bit does not indicate if
there is data in the transmit shift register.
state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the
transmit holding register is empty. - If the FIFO is enabled, this bit is
set when the transmit FIFO is empty. This bit does not indicate if
there is data in the transmit shift register.
6
RXFF
R
X
UART Receive FIFO Full: The meaning of this bit depends on the
state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the
receive holding register is full. - If the FIFO is enabled, this bit is set
when the receive FIFO is full.
state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the
receive holding register is full. - If the FIFO is enabled, this bit is set
when the receive FIFO is full.
5
TXFF
R
X
UART Transmit FIFO Full: Transmit FIFO full. The meaning of this
bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this
bit is set when the transmit holding register is full. - If the FIFO is
enabled, this bit is set when the transmit FIFO is full.
bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this
bit is set when the transmit holding register is full. - If the FIFO is
enabled, this bit is set when the transmit FIFO is full.
4
RXFE
R
1h
UART Receive FIFO Empty: Receive FIFO empty. The meaning of
this bit depends on the state of LCRH.FEN. - If the FIFO is disabled,
this bit is set when the receive holding register is empty. - If the FIFO
is enabled, this bit is set when the receive FIFO is empty.
this bit depends on the state of LCRH.FEN. - If the FIFO is disabled,
this bit is set when the receive holding register is empty. - If the FIFO
is enabled, this bit is set when the receive FIFO is empty.
3
BUSY
R
X
UART Busy: If this bit is set to 1, the UART is busy transmitting data.
This bit remains set until the complete byte, including all the stop
bits, has been sent from the shift register. This bit is set as soon as
the transmit FIFO becomes non-empty, regardless of whether the
UART is enabled or not.
This bit remains set until the complete byte, including all the stop
bits, has been sent from the shift register. This bit is set as soon as
the transmit FIFO becomes non-empty, regardless of whether the
UART is enabled or not.
2-1
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
CTS
R
0h
Clear To Send: This bit is the complement of the active-low UART
CTS input pin. That is, the bit is 1 when CTS input pin is LOW.
CTS input pin. That is, the bit is 1 when CTS input pin is LOW.
1340
Universal Asynchronous Receivers and Transmitters (UARTS)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated