Texas Instruments CC2650DK 사용자 설명서
UARTS Registers
19.7.1.2 RSR Register (Offset = 4h) [reset = X]
RSR is shown in
and described in
.
Status This register is mapped to the same address as ECR register. Reads from this address are
associated with RSR register and return the receive status. Writes to this address are associated with
ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is
read from this register, then the status information for break, framing and parity corresponds to the data
character read from the Data Register, DR prior to reading the RSR. The status information for overrun is
set immediately when an overrun condition occurs.
associated with RSR register and return the receive status. Writes to this address are associated with
ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is
read from this register, then the status information for break, framing and parity corresponds to the data
character read from the Data Register, DR prior to reading the RSR. The status information for overrun is
set immediately when an overrun condition occurs.
Figure 19-5. RSR Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
OE
BE
PE
FE
R-X
R-X
R-X
R-X
R-X
Table 19-5. RSR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-4
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
3
OE
R
X
UART Overrun Error: This bit is set to 1 if data is received and the
receive FIFO is already full. The FIFO contents remain valid because
no more data is written when the FIFO is full, , only the contents of
the shift register are overwritten. This is cleared to 0 once there is an
empty space in the FIFO and a new character can be written to it.
receive FIFO is already full. The FIFO contents remain valid because
no more data is written when the FIFO is full, , only the contents of
the shift register are overwritten. This is cleared to 0 once there is an
empty space in the FIFO and a new character can be written to it.
2
BE
R
X
UART Break Error: This bit is set to 1 if a break condition was
detected, indicating that the received data input (UARTRXD input
pin) was held LOW for longer than a full-word transmission time
(defined as start, data, parity and stop bits). When a break occurs, a
0 character is loaded into the FIFO. The next character is enabled
after the receive data input (UARTRXD input pin) goes to a 1
(marking state), and the next valid start bit is received.
detected, indicating that the received data input (UARTRXD input
pin) was held LOW for longer than a full-word transmission time
(defined as start, data, parity and stop bits). When a break occurs, a
0 character is loaded into the FIFO. The next character is enabled
after the receive data input (UARTRXD input pin) goes to a 1
(marking state), and the next valid start bit is received.
1
PE
R
X
UART Parity Error: When set to 1, it indicates that the parity of the
received data character does not match the parity that the
LCRH.EPS and LCRH.SPS select.
received data character does not match the parity that the
LCRH.EPS and LCRH.SPS select.
0
FE
R
X
UART Framing Error: When set to 1, it indicates that the received
character did not have a valid stop bit (a valid stop bit is 1).
character did not have a valid stop bit (a valid stop bit is 1).
1338
Universal Asynchronous Receivers and Transmitters (UARTS)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated