Texas Instruments CC2650DK 사용자 설명서
UARTS Registers
19.7.1.11 RIS Register (Offset = 3Ch) [reset = X]
RIS is shown in
and described in
.
Raw Interrupt Status
Figure 19-14. RIS Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
OERIS
BERIS
PERIS
R-X
R-X
R-X
R-X
7
6
5
4
3
2
1
0
FERIS
RTRIS
TXRIS
RXRIS
RESERVED
CTSRMIS
RESERVED
R-X
R-X
R-X
R-X
R-3h
R-0h
R-1h
Table 19-14. RIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-11
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
10
OERIS
R
X
Overrun error interrupt status: This field returns the raw interrupt
state of UART's overrun error interrupt. Overrun error occurs if data
is received and the receive FIFO is full.
state of UART's overrun error interrupt. Overrun error occurs if data
is received and the receive FIFO is full.
9
BERIS
R
X
Break error interrupt status: This field returns the raw interrupt state
of UART's break error interrupt. Break error is set when a break
condition is detected, indicating that the received data input
(UARTRXD input pin) was held LOW for longer than a full-word
transmission time (defined as start, data, parity and stop bits).
of UART's break error interrupt. Break error is set when a break
condition is detected, indicating that the received data input
(UARTRXD input pin) was held LOW for longer than a full-word
transmission time (defined as start, data, parity and stop bits).
8
PERIS
R
X
Parity error interrupt status: This field returns the raw interrupt state
of UART's parity error interrupt. Parity error is set if the parity of the
received data character does not match the parity that the
LCRH.EPS and LCRH.SPS select.
of UART's parity error interrupt. Parity error is set if the parity of the
received data character does not match the parity that the
LCRH.EPS and LCRH.SPS select.
7
FERIS
R
X
Framing error interrupt status: This field returns the raw interrupt
state of UART's framing error interrupt. Framing error is set if the
received character does not have a valid stop bit (a valid stop bit is
1).
state of UART's framing error interrupt. Framing error is set if the
received character does not have a valid stop bit (a valid stop bit is
1).
6
RTRIS
R
X
Receive timeout interrupt status: This field returns the raw interrupt
state of UART's receive timeout interrupt. The receive timeout
interrupt is asserted when the receive FIFO is not empty, and no
more data is received during a 32-bit period. The receive timeout
interrupt is cleared either when the FIFO becomes empty through
reading all the data, or when a 1 is written to ICR.RTIC. The raw
interrupt for receive timeout cannot be set unless the mask is set
(IMSC.RTIM = 1). This is because the mask acts as an enable for
power saving. That is, the same status can be read from MIS.RTMIS
and RTRIS.
state of UART's receive timeout interrupt. The receive timeout
interrupt is asserted when the receive FIFO is not empty, and no
more data is received during a 32-bit period. The receive timeout
interrupt is cleared either when the FIFO becomes empty through
reading all the data, or when a 1 is written to ICR.RTIC. The raw
interrupt for receive timeout cannot be set unless the mask is set
(IMSC.RTIM = 1). This is because the mask acts as an enable for
power saving. That is, the same status can be read from MIS.RTMIS
and RTRIS.
1348
Universal Asynchronous Receivers and Transmitters (UARTS)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated