Texas Instruments CC2650DK 사용자 설명서
UARTS Registers
Table 19-14. RIS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
TXRIS
R
X
Transmit interrupt status: This field returns the raw interrupt state of
UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN =
1), the transmit interrupt is asserted if the number of bytes in
transmit FIFO is equal to or lower than the programmed trigger level
(IFLS.TXSEL). The transmit interrupt is cleared by writing data to the
transmit FIFO until it becomes greater than the trigger level, or by
clearing the interrupt through ICR.TXIC. When FIFOs are disabled
(LCRH.FEN = 0), that is they have a depth of one location, the
transmit interrupt is asserted if there is no data present in the
transmitters single location. It is cleared by performing a single write
to the transmit FIFO, or by clearing the interrupt through ICR.TXIC.
UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN =
1), the transmit interrupt is asserted if the number of bytes in
transmit FIFO is equal to or lower than the programmed trigger level
(IFLS.TXSEL). The transmit interrupt is cleared by writing data to the
transmit FIFO until it becomes greater than the trigger level, or by
clearing the interrupt through ICR.TXIC. When FIFOs are disabled
(LCRH.FEN = 0), that is they have a depth of one location, the
transmit interrupt is asserted if there is no data present in the
transmitters single location. It is cleared by performing a single write
to the transmit FIFO, or by clearing the interrupt through ICR.TXIC.
4
RXRIS
R
X
Receive interrupt status: This field returns the raw interrupt state of
UART's receive interrupt. When FIFOs are enabled (LCRH.FEN =
1), the receive interrupt is asserted if the receive FIFO reaches the
programmed trigger level (IFLS.RXSEL). The receive interrupt is
cleared by reading data from the receive FIFO until it becomes less
than the trigger level, or by clearing the interrupt through ICR.RXIC.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth
of one location, the receive interrupt is asserted if data is received
thereby filling the location. The receive interrupt is cleared by
performing a single read of the receive FIFO, or by clearing the
interrupt through ICR.RXIC.
UART's receive interrupt. When FIFOs are enabled (LCRH.FEN =
1), the receive interrupt is asserted if the receive FIFO reaches the
programmed trigger level (IFLS.RXSEL). The receive interrupt is
cleared by reading data from the receive FIFO until it becomes less
than the trigger level, or by clearing the interrupt through ICR.RXIC.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth
of one location, the receive interrupt is asserted if data is received
thereby filling the location. The receive interrupt is cleared by
performing a single read of the receive FIFO, or by clearing the
interrupt through ICR.RXIC.
3-2
RESERVED
R
3h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
CTSRMIS
R
0h
Clear to Send (CTS) modem interrupt status: This field returns the
raw interrupt state of UART's clear to send interrupt.
raw interrupt state of UART's clear to send interrupt.
0
RESERVED
R
1h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1349
SWCU117A – February 2015 – Revised March 2015
Universal Asynchronous Receivers and Transmitters (UARTS)
Copyright © 2015, Texas Instruments Incorporated