Texas Instruments CC2650DK 사용자 설명서
SSIn_Clk
SSIn_Fss
SSIn_Rx
SSIn_Tx
Q
MSB
Q
MSB
LSB
LSB
4 to 16 bits
Q
Functional Description
The data is now captured on the rising edges and propagated on the falling edges of the SSIn_CLK
signal.
signal.
For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned
to its IDLE high state one SSIn_CLK period after the last bit is captured.
to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data
word transfer because the slave-select pin freezes the data in its serial peripheral register and does not
allow altering of the data if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the
slave device between each data transfer to enable the serial peripheral data write. When the continuous
transfer completes, the SSIn_FSS pin is returned to its IDLE state one SSIn_CLK period after the last bit
is captured.
word transfer because the slave-select pin freezes the data in its serial peripheral register and does not
allow altering of the data if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the
slave device between each data transfer to enable the serial peripheral data write. When the continuous
transfer completes, the SSIn_FSS pin is returned to its IDLE state one SSIn_CLK period after the last bit
is captured.
20.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
shows the transfer signal sequence for Motorola SPI format with SPO = 0 and SPH = 1, which
covers both single and continuous transfers.
Figure 20-6. Motorola SPI Frame Format With SPO = 0 and SPH = 1
Note: Q is undefined.
In this configuration, during idle periods:
•
SSIn_CLK is forced low.
•
SSIn_FSS is forced high.
•
The transmit data line SSIn_TX is arbitrarily forced low.
•
When the SSI is configured as a master, it enables the SSIn_CLK pad.
•
When the SSI is configured as a slave, it disables the SSIn_CLK pad.
If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal goes low at the start of
transmission. The master SSIn_TX output is enabled. After an additional one-half SSIn_CLK period, both
master and slave valid data are enabled onto their respective transmission lines. At the same time,
SSIn_CLK is enabled with a rising-edge transition. Data is then captured on the falling edges and
propagated on the rising edges of the SSIn_CLK signal.
transmission. The master SSIn_TX output is enabled. After an additional one-half SSIn_CLK period, both
master and slave valid data are enabled onto their respective transmission lines. At the same time,
SSIn_CLK is enabled with a rising-edge transition. Data is then captured on the falling edges and
propagated on the rising edges of the SSIn_CLK signal.
For a single-word transfer, after all bits are transferred, the SSIn_FSS line is returned to its IDLE high
state one SSIn_CLK period after the last bit is captured.
state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transfers, the SSIn_FSS pin is held low between successive data words and
terminates like a single-word transfer.
terminates like a single-word transfer.
1360
Synchronous Serial Interface (SSI)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated