Texas Instruments CC2650DK 사용자 설명서
SSI Registers
20.7.1.7 RIS Register (Offset = 18h) [reset = X]
RIS is shown in
and described in
.
Raw Interrupt Status
Figure 20-19. RIS Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
TXRIS
RXRIS
RTRIS
RORRIS
R-X
R-1h
R-X
R-X
R-X
Table 20-9. RIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-4
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
3
TXRIS
R
1h
Raw transmit FIFO interrupt status: The transmit interrupt is asserted
when there are four or fewer valid entries in the transmit FIFO. The
transmit interrupt is not qualified with the SSI enable signal.
Therefore one of the following ways can be used: - data can be
written to the transmit FIFO prior to enabling the SSI and the
interrupts. - SSI and interrupts can be enabled so that data can be
written to the transmit FIFO by an interrupt service routine.
when there are four or fewer valid entries in the transmit FIFO. The
transmit interrupt is not qualified with the SSI enable signal.
Therefore one of the following ways can be used: - data can be
written to the transmit FIFO prior to enabling the SSI and the
interrupts. - SSI and interrupts can be enabled so that data can be
written to the transmit FIFO by an interrupt service routine.
2
RXRIS
R
X
Raw interrupt state of receive FIFO interrupt: The receive interrupt is
asserted when there are four or more valid entries in the receive
FIFO.
asserted when there are four or more valid entries in the receive
FIFO.
1
RTRIS
R
X
Raw interrupt state of receive timeout interrupt: The receive timeout
interrupt is asserted when the receive FIFO is not empty and SSI
has remained idle for a fixed 32 bit period. This mechanism can be
used to notify the user that data is still present in the receive FIFO
and requires servicing. This interrupt is deasserted if the receive
FIFO becomes empty by subsequent reads, or if new data is
received on RXD. It can also be cleared by writing to ICR.RTIC.
interrupt is asserted when the receive FIFO is not empty and SSI
has remained idle for a fixed 32 bit period. This mechanism can be
used to notify the user that data is still present in the receive FIFO
and requires servicing. This interrupt is deasserted if the receive
FIFO becomes empty by subsequent reads, or if new data is
received on RXD. It can also be cleared by writing to ICR.RTIC.
0
RORRIS
R
X
Raw interrupt state of receive overrun interrupt: The receive overrun
interrupt is asserted when the FIFO is already full and an additional
data frame is received, causing an overrun of the FIFO. Data is over-
written in the receive shift register, but not the FIFO so the FIFO
contents stay valid. It can also be cleared by writing to ICR.RORIC.
interrupt is asserted when the FIFO is already full and an additional
data frame is received, causing an overrun of the FIFO. Data is over-
written in the receive shift register, but not the FIFO so the FIFO
contents stay valid. It can also be cleared by writing to ICR.RORIC.
1374
Synchronous Serial Interface (SSI)
SWCU117A – February 2015 – Revised March 2015
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