Texas Instruments CC2650DK 사용자 설명서
SSI Registers
20.7.1.8 MIS Register (Offset = 1Ch) [reset = X]
MIS is shown in
and described in
Masked Interrupt Status
Figure 20-20. MIS Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
TXMIS
RXMIS
RTMIS
RORMIS
R-X
R-X
R-X
R-X
R-X
Table 20-10. MIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-4
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
3
TXMIS
R
X
Masked interrupt state of transmit FIFO interrupt: This field returns
the masked interrupt state of transmit FIFO interrupt which is the
AND product of raw interrupt state RIS.TXRIS and the mask setting
IMSC.TXIM.
the masked interrupt state of transmit FIFO interrupt which is the
AND product of raw interrupt state RIS.TXRIS and the mask setting
IMSC.TXIM.
2
RXMIS
R
X
Masked interrupt state of receive FIFO interrupt: This field returns
the masked interrupt state of receive FIFO interrupt which is the
AND product of raw interrupt state RIS.RXRIS and the mask setting
IMSC.RXIM.
the masked interrupt state of receive FIFO interrupt which is the
AND product of raw interrupt state RIS.RXRIS and the mask setting
IMSC.RXIM.
1
RTMIS
R
X
Masked interrupt state of receive timeout interrupt: This field returns
the masked interrupt state of receive timeout interrupt which is the
AND product of raw interrupt state RIS.RTRIS and the mask setting
IMSC.RTIM.
the masked interrupt state of receive timeout interrupt which is the
AND product of raw interrupt state RIS.RTRIS and the mask setting
IMSC.RTIM.
0
RORMIS
R
X
Masked interrupt state of receive overrun interrupt: This field returns
the masked interrupt state of receive overrun interrupt which is the
AND product of raw interrupt state RIS.RORRIS and the mask
setting IMSC.RORIM.
the masked interrupt state of receive overrun interrupt which is the
AND product of raw interrupt state RIS.RORRIS and the mask
setting IMSC.RORIM.
1375
SWCU117A – February 2015 – Revised March 2015
Synchronous Serial Interface (SSI)
Copyright © 2015, Texas Instruments Incorporated