Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.17 NVIC_IPR0 Register (Offset = 400h) [reset = X]
NVIC_IPR0 is shown in
and described in
.
Irq 0 to 3 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts.
0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers
changes based on the setting in AIRCR.PRIGROUP.
0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers
changes based on the setting in AIRCR.PRIGROUP.
Figure 2-87. NVIC_IPR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRI_3
PRI_2
PRI_1
PRI_0
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-113. NVIC_IPR0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PRI_3
R/W
X
Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details).
23-16
PRI_2
R/W
X
Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details).
15-8
PRI_1
R/W
X
Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details).
7-0
PRI_0
R/W
X
Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details).
157
SWCU117A – February 2015 – Revised March 2015
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