Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.19 NVIC_IPR2 Register (Offset = 408h) [reset = X]
NVIC_IPR2 is shown in
and described in
.
Irq 8 to 11 Priority This register is used to assign a priority from 0 to 255 to each of the available
interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority
Registers changes based on the setting in AIRCR.PRIGROUP.
interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority
Registers changes based on the setting in AIRCR.PRIGROUP.
Figure 2-89. NVIC_IPR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRI_11
PRI_10
PRI_9
PRI_8
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-115. NVIC_IPR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PRI_11
R/W
X
Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details).
23-16
PRI_10
R/W
X
Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details).
15-8
PRI_9
R/W
X
Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details).
7-0
PRI_8
R/W
X
Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details).
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SWCU117A – February 2015 – Revised March 2015
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