Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
Table 2-132. CFSR Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15
BFARVALID
R/W
X
This bit is set if the Bus Fault Address Register (BFAR) contains a
valid address. This is true after a bus fault where the address is
known. Other faults can clear this bit, such as a Mem Manage fault
occurring later. If a Bus fault occurs that is escalated to a Hard Fault
because of priority, the Hard Fault handler must clear this bit. This
prevents problems if returning to a stacked active Bus fault handler
whose BFAR value has been overwritten.
valid address. This is true after a bus fault where the address is
known. Other faults can clear this bit, such as a Mem Manage fault
occurring later. If a Bus fault occurs that is escalated to a Hard Fault
because of priority, the Hard Fault handler must clear this bit. This
prevents problems if returning to a stacked active Bus fault handler
whose BFAR value has been overwritten.
14-13
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
12
STKERR
R/W
X
Stacking from exception has caused one or more bus faults. The SP
is still adjusted and the values in the context area on the stack might
be incorrect. BFAR is not written.
is still adjusted and the values in the context area on the stack might
be incorrect. BFAR is not written.
11
UNSTKERR
R/W
X
Unstack from exception return has caused one or more bus faults.
This is chained to the handler, so that the original return stack is still
present. SP is not adjusted from failing return and new save is not
performed. BFAR is not written.
This is chained to the handler, so that the original return stack is still
present. SP is not adjusted from failing return and new save is not
performed. BFAR is not written.
10
IMPRECISERR
R/W
X
Imprecise data bus error. It is a BusFault, but the Return PC is not
related to the causing instruction. This is not a synchronous fault.
So, if detected when the priority of the current activation is higher
than the Bus Fault, it only pends. Bus fault activates when returning
to a lower priority activation. If a precise fault occurs before returning
to a lower priority exception, the handler detects both
IMPRECISERR set and one of the precise fault status bits set at the
same time. BFAR is not written.
related to the causing instruction. This is not a synchronous fault.
So, if detected when the priority of the current activation is higher
than the Bus Fault, it only pends. Bus fault activates when returning
to a lower priority activation. If a precise fault occurs before returning
to a lower priority exception, the handler detects both
IMPRECISERR set and one of the precise fault status bits set at the
same time. BFAR is not written.
9
PRECISERR
R/W
X
Precise data bus error return.
8
IBUSERR
R/W
X
Instruction bus error flag. This flag is set by a prefetch error. The
fault stops on the instruction, so if the error occurs under a branch
shadow, no fault occurs. BFAR is not written.
fault stops on the instruction, so if the error occurs under a branch
shadow, no fault occurs. BFAR is not written.
7
MMARVALID
R/W
X
Memory Manage Address Register (MMFAR) address valid flag. A
later-arriving fault, such as a bus fault, can clear a memory manage
fault.. If a MemManage fault occurs that is escalated to a Hard Fault
because of priority, the Hard Fault handler must clear this bit. This
prevents problems on return to a stacked active MemManage
handler whose MMFAR value has been overwritten.
later-arriving fault, such as a bus fault, can clear a memory manage
fault.. If a MemManage fault occurs that is escalated to a Hard Fault
because of priority, the Hard Fault handler must clear this bit. This
prevents problems on return to a stacked active MemManage
handler whose MMFAR value has been overwritten.
6-5
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
4
MSTKERR
R/W
X
Stacking from exception has caused one or more access violations.
The SP is still adjusted and the values in the context area on the
stack might be incorrect. MMFAR is not written.
The SP is still adjusted and the values in the context area on the
stack might be incorrect. MMFAR is not written.
3
MUNSTKERR
R/W
X
Unstack from exception return has caused one or more access
violations. This is chained to the handler, so that the original return
stack is still present. SP is not adjusted from failing return and new
save is not performed. MMFAR is not written.
violations. This is chained to the handler, so that the original return
stack is still present. SP is not adjusted from failing return and new
save is not performed. MMFAR is not written.
2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
DACCVIOL
R/W
X
Data access violation flag. Attempting to load or store at a location
that does not permit the operation sets this flag. The return PC
points to the faulting instruction. This error loads MMFAR with the
address of the attempted access.
that does not permit the operation sets this flag. The return PC
points to the faulting instruction. This error loads MMFAR with the
address of the attempted access.
0
IACCVIOL
R/W
X
Instruction access violation flag. Attempting to fetch an instruction
from a location that does not permit execution sets this flag. This
occurs on any access to an XN region, even when the MPU is
disabled or not present. The return PC points to the faulting
instruction. MMFAR is not written.
from a location that does not permit execution sets this flag. This
occurs on any access to an XN region, even when the MPU is
disabled or not present. The return PC points to the faulting
instruction. MMFAR is not written.
179
SWCU117A – February 2015 – Revised March 2015
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