Texas Instruments CC2650DK 사용자 설명서
Cortex-M3 Processor Registers
2.7.4.37 HFSR Register (Offset = D2Ch) [reset = X]
HFSR is shown in
and described in
.
Hard Fault Status This register is used to obtain information about events that activate the Hard Fault
handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit.
handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit.
Figure 2-107. HFSR Register
31
30
29
28
27
26
25
24
DEBUGEVT
FORCED
RESERVED
R/W1C-X
R/W1C-X
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
VECTTBL
RESERVED
R/W-X
R/W1C-X
R/W-X
Table 2-133. HFSR Register Field Descriptions
Bit
Field
Type
Reset
Description
31
DEBUGEVT
R/W1C
X
This bit is set if there is a fault related to debug. This is only possible
when halting debug is not enabled. For monitor enabled debug, it
only happens for BKPT when the current priority is higher than the
monitor. When both halting and monitor debug are disabled, it only
happens for debug events that are not ignored (minimally, BKPT).
The Debug Fault Status Register is updated.
when halting debug is not enabled. For monitor enabled debug, it
only happens for BKPT when the current priority is higher than the
monitor. When both halting and monitor debug are disabled, it only
happens for debug events that are not ignored (minimally, BKPT).
The Debug Fault Status Register is updated.
30
FORCED
R/W1C
X
Hard Fault activated because a Configurable Fault was received and
cannot activate because of priority or because the Configurable Fault
is disabled. The Hard Fault handler then has to read the other fault
status registers to determine cause.
cannot activate because of priority or because the Configurable Fault
is disabled. The Hard Fault handler then has to read the other fault
status registers to determine cause.
29-2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
VECTTBL
R/W1C
X
This bit is set if there is a fault because of vector table read on
exception processing (Bus Fault). This case is always a Hard Fault.
The return PC points to the pre-empted instruction.
exception processing (Bus Fault). This case is always a Hard Fault.
The return PC points to the pre-empted instruction.
0
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
180
SWCU117A – February 2015 – Revised March 2015
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