Texas Instruments CC2650DK 사용자 설명서
Coretex-M3 Core Registers
Table 2-20. Program Status Register (PSR)
Address Offset
Reset
0x0100 0000
Physical Address
Instance
Description
Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions:
• Application Program Status Register (APSR), bits 31:27
• Execution Program Status Register (EPSR), bits 26:24, 15:10
• Interrupt Program Status Register (IPSR), bits 6:0
The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be accessed in privileged or
unprivileged mode.
unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction
(ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using
the MSR instruction always return 0. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see
(ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using
the MSR instruction always return 0. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see
, Exception Entry and
Return).
IPSR contains the exception type number of the current ISR.
These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument
to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be
written to using APSR with the MSR instruction.
to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be
written to using APSR with the MSR instruction.
shows the possible register combinations for the PSR. See the MRS and MSR
instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual for more information about how to access the program
status registers.
status registers.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
N
Z
C
V
Q
ICI / IT
RESERVED
ICI / IT
ISRNUM
THUMB
RESERVED
Bits
Field Name
Description
Type
Reset
31
N
APSR Negative or Less Flag
R/W
0
Value
Description
1
The previous operation result was negative or less than.
0
The previous operation result was positive, zero, greater
than, or equal
than, or equal
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR.
30
Z
APSR Zero Flag
R/W
0
Value
Description
1
The previous operation result was zero.
0
The previous operation result was nonzero.
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR.
29
C
APSR Carry or Borrow Flag
R/W
0
Value
Description
1
The previous add operation resulted in a carry bit or the
previous subtract operation did not result in a borrow bit.
previous subtract operation did not result in a borrow bit.
0
The previous add operation did not result in a carry bit or
the previous subtract operation resulted in a borrow bit.
the previous subtract operation resulted in a borrow bit.
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR.
28
V
APSR Overflow Flag
R/W
0
Value
Description
41
SWCU117A – February 2015 – Revised March 2015
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