Texas Instruments CC2650DK 사용자 설명서
Coretex-M3 Core Registers
Bits
Field Name
Description
Type
Reset
1
The previous operation resulted in an overflow.
0
The previous operation did not result in an overflow.
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR.
27
Q
APSR Sticky Overflow and Saturation Flag
R/W
0
Value
Description
1
Overflow or Saturation has occurred. (set by SSAT or
USAT instructions).
USAT instructions).
0
Overflow or saturation has not occurred since reset or
since the bit was last cleared.
since the bit was last cleared.
The value of this bit is meaningful only when accessing PSR or
APSR.
This flag is sticky, in that, when set by an instruction it remains set
until explicitly cleared using an MSR instruction.
APSR.
This flag is sticky, in that, when set by an instruction it remains set
until explicitly cleared using an MSR instruction.
26:25
ICI / IT
EPSR ICI / IT status
RO
0x0
These bits, along with bits 15:10, contain the ICI field for an
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When EPSR holds the ICI
execution state, bits 26:25 are 0. The If-Then block contains up to
four instructions following an IT instruction. Each instruction in the
block is conditional. The conditions for the instructions are either all
the same, or some can be the inverse of others. See the Cortex™-
M3 Instruction Set Technical User's Manual for more information.
The value of this field is meaningful only when accessing PSR or
EPSR.
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When EPSR holds the ICI
execution state, bits 26:25 are 0. The If-Then block contains up to
four instructions following an IT instruction. Each instruction in the
block is conditional. The conditions for the instructions are either all
the same, or some can be the inverse of others. See the Cortex™-
M3 Instruction Set Technical User's Manual for more information.
The value of this field is meaningful only when accessing PSR or
EPSR.
24
THUMB
EPSR Thumb state
RO
1
This bit indicates the Thumb state and must always be set. The
following can clear the THUMB bit:
following can clear the THUMB bit:
• The BLX, BX and POP{PC} instructions
• Restoration from the stacked xPSR value on an exception return
• Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a
fault or lockup. For more information, see
Attempting to execute instructions when this bit is clear results in a
fault or lockup. For more information, see
, Lockup.
The value of this bit is meaningful only when accessing PSR or
EPSR.
EPSR.
23:16
RESERVED
Reserved
RO
0x00
15:10
ICI / IT
EPSR ICI / IT status
RO
0x0
These bits, along with bits 26:25, contain the Interruptible-
Continuable Instruction (ICI) field for an interrupted load multiple or
store multiple instruction or the execution state bits of the IT
instruction. When an interrupt occurs during the execution of an
LDM, STM, PUSH, or POP instruction, the processor stops the load
multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits
15:12. After servicing the interrupt, the processor returns to the
register pointed to by bits 15:12 and resumes execution of the
multiple load or store instruction. When EPSR holds the ICI
execution state, bits 11:10 are 0. The If-Then block contains up to
four instructions following a 16-bit IT instruction. Each instruction in
the block is conditional. The conditions for the instructions are
either all the same, or some can be the inverse of others. See the
Cortex™-M3 Instruction Set Technical User's Manual for more
information. The value of this field is meaningful only when
accessing PSR or EPSR.
Continuable Instruction (ICI) field for an interrupted load multiple or
store multiple instruction or the execution state bits of the IT
instruction. When an interrupt occurs during the execution of an
LDM, STM, PUSH, or POP instruction, the processor stops the load
multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits
15:12. After servicing the interrupt, the processor returns to the
register pointed to by bits 15:12 and resumes execution of the
multiple load or store instruction. When EPSR holds the ICI
execution state, bits 11:10 are 0. The If-Then block contains up to
four instructions following a 16-bit IT instruction. Each instruction in
the block is conditional. The conditions for the instructions are
either all the same, or some can be the inverse of others. See the
Cortex™-M3 Instruction Set Technical User's Manual for more
information. The value of this field is meaningful only when
accessing PSR or EPSR.
9:7
RESERVED
Software must not rely on the value of a reserved bit. To provide
RO
0x0
compatibility with future products, the value of a reserved bit must
be preserved across a read-modify-write operation.
be preserved across a read-modify-write operation.
6:0
ISRNUM
IPSR ISR Number
RO
0x00
This field contains the exception type number of the current ISR.
Value
Description
0x00
Thread mode
0x01
Reserved
0x02
NMI
42
SWCU117A – February 2015 – Revised March 2015
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