Texas Instruments CC2650DK 사용자 설명서
PRCM Registers
6.2.2.1
PWRCTL Register (Offset = 0h) [reset = X]
PWRCTL is shown in
and described in
.
Power Management This register controls bitfields for setting low level power management features such
as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled /
disabled.
as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled /
disabled.
Figure 6-64. PWRCTL Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
DCDC_ACTIVE
EXT_REG_MO
DCDC_EN
DE
R/W-X
R/W-X
R-X
R/W-X
Table 6-67. PWRCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-3
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
DCDC_ACTIVE
R/W
X
Select to use DCDC regulator for VDDR in active mode 0: Use
GLDO for regulation of VDDRin active mode. 1: Use DCDC for
regulation of VDDRin active mode.
GLDO for regulation of VDDRin active mode. 1: Use DCDC for
regulation of VDDRin active mode.
1
EXT_REG_MODE
R
X
Status of source for VDDRsupply: 0: DCDC/GLDO are generating
VDDR 1: DCDC/GLDO are bypassed, external regulator supplies
VDDR
VDDR 1: DCDC/GLDO are bypassed, external regulator supplies
VDDR
0
DCDC_EN
R/W
X
Select to use DCDC regulator during recharge of VDDR 0: Use
GLDO for recharge of VDDR 1: Use DCDC for recharge of VDDR
Note: This bitfield should be set to the same as DCDC_ACTIVE
GLDO for recharge of VDDR 1: Use DCDC for recharge of VDDR
Note: This bitfield should be set to the same as DCDC_ACTIVE
489
SWCU117A – February 2015 – Revised March 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated