Texas Instruments CC2650DK 사용자 설명서
PRCM Registers
Table 6-68. RESETCTL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
11
VDDS_LOSS_EN_OVR
R/W
X
Override of VDDS_LOSS_EN 0: Brown out detect of VDDS is
ignored, unless VDDS_LOSS_EN=1 1: Brown out detect of VDDS
generates system reset (regardless of VDDS_LOSS_EN) This bit
can be locked
ignored, unless VDDS_LOSS_EN=1 1: Brown out detect of VDDS
generates system reset (regardless of VDDS_LOSS_EN) This bit
can be locked
10
VDDR_LOSS_EN_OVR
R/W
X
Override of VDDR_LOSS_EN 0: Brown out detect of VDDR is
ignored, unless VDDR_LOSS_EN=1 1: Brown out detect of VDDR
generates system reset (regardless of VDDR_LOSS_EN) This bit
can be locked
ignored, unless VDDR_LOSS_EN=1 1: Brown out detect of VDDR
generates system reset (regardless of VDDR_LOSS_EN) This bit
can be locked
9
VDD_LOSS_EN_OVR
R/W
X
Override of VDD_LOSS_EN 0: Brown out detect of VDD is ignored,
unless VDD_LOSS_EN=1 1: Brown out detect of VDD generates
system reset (regardless of VDD_LOSS_EN) This bit can be locked
unless VDD_LOSS_EN=1 1: Brown out detect of VDD generates
system reset (regardless of VDD_LOSS_EN) This bit can be locked
8
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7
VDDS_LOSS_EN
R/W
1h
Controls reset generation in case VDDS is lost 0: Brown out detect
of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out
detect of VDDS generates system reset
of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out
detect of VDDS generates system reset
6
VDDR_LOSS_EN
R/W
1h
Controls reset generation in case VDDR is lost 0: Brown out detect
of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out
detect of VDDR generates system reset
of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out
detect of VDDR generates system reset
5
VDD_LOSS_EN
R/W
1h
Controls reset generation in case VDD is lost 0: Brown out detect of
VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect
of VDD generates system reset
VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect
of VDD generates system reset
4
CLK_LOSS_EN
R/W
X
Controls reset generation in case SCLK_LF is lost. (provided that
clock loss detection is enabled by
DDI_0_OSC:CTL0.CLK_LOSS_EN) Note: Clock loss reset
generation must be disabled before SCLK_LF clock source is
changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain
disabled untill the change is confirmed in
DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do so may result in a
spurious system reset. Clock loss reset generation can be disabled
through this bitfield or by clearing
DDI_0_OSC:CTL0.CLK_LOSS_EN 0: Clock loss is ignored 1: Clock
loss generates system reset
clock loss detection is enabled by
DDI_0_OSC:CTL0.CLK_LOSS_EN) Note: Clock loss reset
generation must be disabled before SCLK_LF clock source is
changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain
disabled untill the change is confirmed in
DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do so may result in a
spurious system reset. Clock loss reset generation can be disabled
through this bitfield or by clearing
DDI_0_OSC:CTL0.CLK_LOSS_EN 0: Clock loss is ignored 1: Clock
loss generates system reset
3-1
RESET_SRC
R
X
Shows the source of the last system reset: Occurrence of one of the
reset sources may trigger several other reset sources as essential
parts of the system are undergoing reset. This field will report the
root cause of the reset (not the other resets that are consequence of
the system reset). To support this feature the actual register is not
captured before the reset source being released. If a new reset
source is triggered, in a window of four 32 kHz periods after the
previous has been released, this register may indicate Power on
reset as source.
reset sources may trigger several other reset sources as essential
parts of the system are undergoing reset. This field will report the
root cause of the reset (not the other resets that are consequence of
the system reset). To support this feature the actual register is not
captured before the reset source being released. If a new reset
source is triggered, in a window of four 32 kHz periods after the
previous has been released, this register may indicate Power on
reset as source.
0h = Power on reset
1h = Reset pin
2h = Brown out detect on VDDS
3h = Brown out detect on VDD
4h = Brown out detect on VDDR
5h = Clock loss detect
6h = Software reset via SYSRESET register
7h = Software reset via PRCM warm reset request
0
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
491
SWCU117A – February 2015 – Revised March 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated