Texas Instruments CC2650DK 사용자 설명서
GPRAM
ENABLED
SPLIT
Reset
OFF
Invalidating
Invalidating
VIMS Configurations
7.1
VIMS Configurations
7.1.1 VIMS Modes
The VIMS cache RAM block and the Cache block can operate in the following modes:
•
GPRAM
•
CACHE
•
OFF
The current mode is shown in VIMS.STAT.*, and mode switching is controlled through VIMS.CTL.MODE.
The mode transitions are shown in
The mode transitions are shown in
. Lines in black are software initiated changes through
CTL.MODE. Lines in brown are hardware initiated changes. The invalidating state is a transition state
controlled by hardware. Invalidation clears the entire content of the RAM block and takes 1029 clock
periods to perform.
controlled by hardware. Invalidation clears the entire content of the RAM block and takes 1029 clock
periods to perform.
Figure 7-2. VIMS Mode Switching Flowchart
Once a mode change is initiated, shown in STATUS.MODE_CHANGING, the mode change must
complete before another mode change can be initiated. The CTL.MODE is blocked for updates during a
mode change.
complete before another mode change can be initiated. The CTL.MODE is blocked for updates during a
mode change.
7.1.1.1
GPRAM Mode
In GPRAM mode, the RAM block functions as a general-purpose RAM. The Flash block has no cache
support, and all accesses to the flash are routed directly to the Flash block.
support, and all accesses to the flash are routed directly to the Flash block.
531
SWCU117A – February 2015 – Revised March 2015
Versatile Instruction Memory System (VIMS)
Copyright © 2015, Texas Instruments Incorporated