Texas Instruments CC2650DK 사용자 설명서
GP-RAM
rom
FLASH
icode/dcode
SYSCODE and
USERCODE
address space
BROM
address space
sysbus
icode/dcode
sysbus
GP-RAM
rom
FLASH
GPRAM
address space
icode/dcode
SYSCODE and
USERCODE
address space
BROM
address space
sysbus
icode/dcode
sysbus
VIMS Configurations
Figure 7-3. VIMS Module in GPRAM Mode
7.1.1.2
Off Mode
In off mode, the RAM block is disabled and cannot be accessed by the CPU or by the system bus. The
Flash block has no cache support, and all accesses to the flash are routed directly to the Flash block.
Flash block has no cache support, and all accesses to the flash are routed directly to the Flash block.
Figure 7-4. VIMS Module in Off Mode
7.1.1.3
Cache Mode
In cache mode, the RAM block will function as an 8-K 4-way random replacement cache for the Flash
block. The GPRAM space is not available in this mode. The cache support is only available for CPU
accesses to the flash SYSCODE address space. System bus accesses to the Flash block and CPU
accesses to the flash USERCODE address space are routed directly to the Flash block.
block. The GPRAM space is not available in this mode. The cache support is only available for CPU
accesses to the flash SYSCODE address space. System bus accesses to the Flash block and CPU
accesses to the flash USERCODE address space are routed directly to the Flash block.
532
Versatile Instruction Memory System (VIMS)
SWCU117A – February 2015 – Revised March 2015
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