Texas Instruments 125 MHz Quad M-LVDS Transceiver Evaluation Board DS91M040EVK/NOPB DS91M040EVK/NOPB 데이터 시트
제품 코드
DS91M040EVK/NOPB
April 14, 2008
Rev. 1.0
© 2008, National Semiconductor Corp.
4
DS91M040 Evaluation in an ATCA Backplane
The following is a recommended procedure for building an evaluation M-LVDS clock distribution network with
DS91M040EVK evaluation boards. The assumption is that the user already has an ATCA backplane. Figure 2
depicts configuration of a generic M-LVDS clock network in an ATCA backplane.
DS91M040EVK evaluation boards. The assumption is that the user already has an ATCA backplane. Figure 2
depicts configuration of a generic M-LVDS clock network in an ATCA backplane.
1. Use two or more DS91M040 evaluation boards and install them at backplane location J20/P20, in the
desired slots.
2. Apply the power to the boards (3.3V typical) between J5 and J6 banana plug receptacles, observe the
value of I
CC,
and compare it with the expected value (refer to the datasheet) to ensure that the devices
are functional.
3. Select the board you want to configure as a clock driver/distributor. This is accomplished by setting DE
and RE* pins to VDD (J1 or J3). Set MDE pin to VDD. Connect a clock source to one of the driver
inputs (J2).
inputs (J2).
4. Configure the remaining boards as clock receivers. This is accomplished by setting DE and RE* pins to
GND (J1 or J3). Set MDE pin to VDD. Set the receiver to either M-LVDS Type 1 (FSEN pins set to
GND) or Type 2 (FSEN pins set to VDD).
GND) or Type 2 (FSEN pins set to VDD).
5. Observe clock waveforms by either connecting receiver LVCMOS output pins (J2) directly to an
oscilloscope or by probing receiver M-LVDS input pins with a differential probe.
Figure 2 - M-LVDS Clock Distribution Network in an ATCA Backplane