Texas Instruments LDC1000EVM - Evaluation Module for Inductance to Digital Converter with Sample PCB Coil LDC1000EVM LDC1000EVM 데이터 시트
제품 코드
LDC1000EVM
1
16
7
6
5
4
3
2
10
11
12
13
14
15
DAP
(GND)
SCLK
SDO
DGND
CFB
VDD
CLDO
XOUT
INB
GND
TBCLK/XIN
INTB
8
9
CSB
SDI
VIO
CFA
INA
SNOSCX2 – SEPTEMBER 2013
CONNECTION DIAGRAM
Figure 4. LDC1000 Pin Diagram
SON-16
Table 1. Pin Description
(1)
PIN NAME
PIN
PIN
FUNCTION
NO.
TYPE
SCLK
1
DO
SPI clock input. SCLK is used to clock-out/clock-in the data from/into the chip
CSB
2
DI
SPI CSB. Multiple devices can be connected on the same SPI bus and CSB can be used to select the
device to be communicated with
SDI
3
DI
SPI Slave Data In (Master Out Slave In). This should be connected to the Master Out Slave In of the
master
VIO
4
P
Digital IO Supply
SDO
5
DO
SPI Slave Data Out (Master In Slave Out).It is high-z when CSB is high
DGND
6
P
Digital ground
CFB
7
A
LDC filter capacitor
CFA
8
A
LDC filter capacitor
INA
9
A
External LC Tank. Connected to external LC tank
INB
10
A
External LC Tank. Connected to external LC tank
GND
11
P
Analog ground
VDD
12
P
Analog supply
CLDO
13
A
LDO bypass capacitor. A 56nF capacitor should be connected from this pin to GND
TBCLK/XIN
14
DI/A
External time-base clock/XTAL. Either an external clock or crystal can be connected
XOUT
15
A
XTAL. Crystal out. Recommended to connect 8Mhz crystal between XIN and XOUT with 20pF cap
from each pin to ground. Should be floating when external clock is used
INTB
16
DO
Configurable interrupt. This pin can be configured to behave in 3 different ways by programing the INT
pin mode register. Either threshold detect, wakeup, or DRDYB
DAP
17
P
Connect to GND
(1)
DO: Digital Output, DI: Digital Input, P: Power, A: Analog
Copyright © 2013, Texas Instruments Incorporated
3
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