Texas Instruments DS90C187 Evaluation Module C187EVK01/NOPB C187EVK01/NOPB 데이터 시트
제품 코드
C187EVK01/NOPB
Setup
SNLU102-May 2012
C187EVK01 User’s Guide
5
J5, J6 – LVCMOS INPUTS for channel A are connected to the 2 x 30 bank of header pins, J5. LVCMOS
inputs for channel B are connected to the 2 x 28 bank of header pins, J6. Note that each LVCMOS signal is
paired with a ground signal. When attaching external test equipment or other hardware to this board it is
important that there be sufficient ground connections to ensure good signal integrity for the input clock and
data waveforms. 50 ohm terminations are provided for each LVCMOS input by default. On a normal PCB
these types of terminations are not needed. These resistors are provided by default to improve signal quality
for long trace lengths during evaluation.
inputs for channel B are connected to the 2 x 28 bank of header pins, J6. Note that each LVCMOS signal is
paired with a ground signal. When attaching external test equipment or other hardware to this board it is
important that there be sufficient ground connections to ensure good signal integrity for the input clock and
data waveforms. 50 ohm terminations are provided for each LVCMOS input by default. On a normal PCB
these types of terminations are not needed. These resistors are provided by default to improve signal quality
for long trace lengths during evaluation.
Figure 4: LVCMOS Input Connections (INA-J5 and INB-J6)
J1 – VDD is the terminal where 1.8V power should be applied.
J2 – GND is the terminal where ground should be applied.