Texas Instruments DS90C187 Evaluation Module C187EVK01/NOPB C187EVK01/NOPB 데이터 시트
제품 코드
C187EVK01/NOPB
Setup
6
C187EVK01 User’s Guide
SNLU102-May 2012
2.2. System Setup
The input power jack (J1) should receive a voltage within the range of 1.71 V to 1.89 V referenced to ground
which should be applied at J2, with JP4 set to LOW. Once, power has been applied to the board, JP4 (PDB
pin) can be set to logic HIGH. After setting the PDB pin to HIGH, 1.8V clock and data can be transmitted to
the EVM. If a cable is connected to J3 and/or J4, the termination resistors (R57, R58, R62, R63, R64
and/or R65, R66, R67, R68, R69) should be removed.
which should be applied at J2, with JP4 set to LOW. Once, power has been applied to the board, JP4 (PDB
pin) can be set to logic HIGH. After setting the PDB pin to HIGH, 1.8V clock and data can be transmitted to
the EVM. If a cable is connected to J3 and/or J4, the termination resistors (R57, R58, R62, R63, R64
and/or R65, R66, R67, R68, R69) should be removed.
2.3. Operation
For proper operation of the DS90C187, JP1, JP2, JP3, JP4, JP5, JP6 and JP7 should be properly configured
by using shorting blocks (jumpers); see Figure 3.
JP1 and JP2 set to the desired device mode (SISO, SIDO or DIDO)
JP3 to LOW for falling clock edge strobe or HIGH for rising clock edge strobe
JP4 to HIGH, after power on
JP5 to LOW for 24-bit color (28-bit data bus) or to HIGH for 18-bit color (21-bit data bus)
JP6 to LOW for reduced VOD swing or HIGH for large VOD swing
JP7 to LOW
After applying power and setting JP4 to HIGH, clock and data can be sent to the DS90C187. When the clock
signal is detected, the DS90C187 will power on and begin to transmit serialized LVDS data.
by using shorting blocks (jumpers); see Figure 3.
JP1 and JP2 set to the desired device mode (SISO, SIDO or DIDO)
JP3 to LOW for falling clock edge strobe or HIGH for rising clock edge strobe
JP4 to HIGH, after power on
JP5 to LOW for 24-bit color (28-bit data bus) or to HIGH for 18-bit color (21-bit data bus)
JP6 to LOW for reduced VOD swing or HIGH for large VOD swing
JP7 to LOW
After applying power and setting JP4 to HIGH, clock and data can be sent to the DS90C187. When the clock
signal is detected, the DS90C187 will power on and begin to transmit serialized LVDS data.
3.
Board Layout
Figure 5, Figure 6 and Figure 7 show the board layout for the C187EVK01 printed circuit board. The EVM
offers jumpers to configure and power on/off the DS90C187. 50 ohm shunt terminations are populated by
default. 100 ohm differential termination resistors are populated by default to allow for easy probing of the
LVDS outputs at J3 and J4.
offers jumpers to configure and power on/off the DS90C187. 50 ohm shunt terminations are populated by
default. 100 ohm differential termination resistors are populated by default to allow for easy probing of the
LVDS outputs at J3 and J4.