Texas Instruments DP83849IFVS Basic product evaluation and customer demo board with FX DP83849IFVS-EVK/NOPB DP83849IFVS-EVK/NOPB 데이터 시트
제품 코드
DP83849IFVS-EVK/NOPB
October 2006
Tung Ngo
v1.1
National Semiconductor Corp
5
DP83849 Demo II Specification
Overview
The DP83849 Demo II is a National Semiconductor demo platform to allow customer evaluation of our
device. While the DP83849 has many advanced and enticing features, this specific board is designed to
demonstrate only a subset of those. The features chosen are the ones that the mainstream customers will
use. Thus we have created an affordable, aesthetic platform to demonstrate the simplicity of designing in a
National Semiconductor DP83849
device. While the DP83849 has many advanced and enticing features, this specific board is designed to
demonstrate only a subset of those. The features chosen are the ones that the mainstream customers will
use. Thus we have created an affordable, aesthetic platform to demonstrate the simplicity of designing in a
National Semiconductor DP83849
.
Target Environment
Equipment that provides standard IEEE 802.3 MII, RMII or SNI interface; e.g. SmartBits/Netcom
Features/Goals
The DP83849 Demo II features:
o
Multiple PHY Addresses – Default are 00h (Port A), 01h (Port B) with increment even values
through 30h (Port A) and odd values through 31h (Port B).
o
9 LEDs – 1 power, 2 INTERRUPT, 6 others (2 LINK, 2 SPEED, 2 ACT/COL) dependant on LED
mode selected
o
Strap Options for Ports (A and B) – ED_EN, MDIX_EN, LED_CFG, Auto-Negotiation
o
FX_EN jumper - Port B only
o
SNI_MODE resistor – Work with MII_MODE pin to set 10 Mb SNI mode. See Strap Options of
datasheet for details.
o
MII_MODE resistor – To set RMII mode. See Strap Options section of datasheet for details.
o
EXTENDER_EN jumper – To set into Extender mode that DP83849IVS and DP83849IFVS
support. See each datasheet respestively for details.
o
CLK2MAC_DIS jumper – To disable clock to MAC output.
o
RESET_N jumper – To allow external reset.
o
PWR_DWN/INT jumper – To set the device into Interrupt mode.
•
Connections for the following interfaces:
o
MII Interface
o
2 x RJ-45, 1 x FX (Port B)
o
Header for “ribbon cable” connection to MII/RMII/SNI
o
JTAG header
o
CLK2MAC header
o
Integrity Interface header
•
Standard PCB layout considerations with regards to clock, MII, and TD/RD
•
On-board clock – Crystal/Oscillator Dual Footprint – 25/50 MHz
o
Crystal (default) – Should be depopulated for RMII option.
o
Oscillator – Resistor stuff option for RMII to bring in external 50 MHz oscillator
•
On-board power supplied by 5V/3V MII connector (A/B), or POE connector (J91)
•
Dual sided component placement
•
Low cost