Texas Instruments DAC5681ZEVM - DAC5681Z Evaluation Module DAC5681ZEVM DAC5681ZEVM 데이터 시트
제품 코드
DAC5681ZEVM
5.5
TSW3100 Configuration and Pattern Generation
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DAC5681/81z/82z EVM Software
The TSW3100 can be loaded with a custom pattern file using the GUI options. For further details on the
file format of the custom pattern, see the TSW3100 Users Guide (
file format of the custom pattern, see the TSW3100 Users Guide (
Figure 12. TSW3100 Pattern Generator and DAC Register Configuration Settings
Table 9. TSW3100 Configuration and Pattern Generation Functionality
Input
Subarea Name
Description
Output
Pattern Selection (1)
Selects Binary and 16-bit signed Integer format. If Binary is selected, the file must comply with
the requirements described on the TSW3100 (
the requirements described on the TSW3100 (
) documentation. If integer format is
File Format
Input
selected, the file must consist of a single column for a real signal or two columns for a
two-channel or complex signal.
two-channel or complex signal.
Browse Button
Input
Navigate to the folder containing the input pattern file name. Select the file to use.
Output Mode (2)
Column Delimiter
Input
Column separator used in the two-channel or complex integer input file. (Not displayed)
Output Level
Input
LVDS or CMOS outputs. Only LVDS is available for the DAC5682z.
Data Format
Input
2's complement or offset binary format.
IP Address
Input
Specify final digit (1, 2, 3, or 4) of the IP address for the TSW3100 pattern generator.
Master or Slave mode. The default state is Master mode. See TSW3100 (
)
TSW3100 State
Input
documentation for more information.
Command Buttons (3)
Load and Start
Input
Load a pattern file and start the TSW3100.
Stop Pattern
Input
Stop the pattern transfer.
Re-start Pattern
Input
Re-start the pattern. A pattern must be loaded in memory for this command to work.
Pattern Generation Results (4)
Command
Output
Shows sequence of commands sent to the TSW3100.
SLAU236A – November 2007 – Revised October 2008
DAC5681/81z/82z EVM
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