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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
8.24 Isochronous Transmit Interrupt Mask Register
The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-
channel basis. Reads from either the set register or the clear register always return the contents of the
isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with
the isochronous transmit interrupt event register bits detailed in
channel basis. Reads from either the set register or the clear register always return the contents of the
isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with
the isochronous transmit interrupt event register bits detailed in
.
OHCI register offset:
98h set register
9Ch clear register
9Ch clear register
Register type:
Read/Set/Clear, Read only
Default value:
0000 00XX
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
8.25 Isochronous Receive Interrupt Event Register
The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous
receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_*
command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt
in the interrupt event register at OHCI offset 80h/84h (see
receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_*
command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt
in the interrupt event register at OHCI offset 80h/84h (see
) has occurred, software can check
this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an
asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding bit in the set
register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the
clear register. See
asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding bit in the set
register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the
clear register. See
for a complete description of the register contents.
OHCI register
A0h
set register
offset:
A4h
clear register (returns the contents of isochronous receive interrupt
event register bit-wise ANDed with the isochronous receive mask
register when read)
event register bit-wise ANDed with the isochronous receive mask
register when read)
Register type:
Read/Set/Clear, Read only
Default value:
0000 000Xh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
Table 8-18. Isochronous Receive Interrupt Event Register Description
BIT
FIELD NAME
TYPE
Description
31-4
RSVD
R
Reserved. Bits 31-4 return 000 0000h when read.
3
isoRecv3
RSC
Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.
2
isoRecv2
RSC
Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.
1
isoRecv1
RSC
Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.
0
isoRecv0
RSC
Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.
Copyright © 2008–2013, Texas Instruments Incorporated
1394 OHCI Memory-Mapped Register Space
153
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