Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM 사용자 매뉴얼

차례

• Table of Contents

  2
• 1  Introduction

  12
  • 1.1 XIO2213B Features

    12
• 2 Overview

  13
  • 2.1 Related Documents

    14
  • 2.2 Documents Conventions

    15
  • 2.3 Ordering Information

    15
  • 2.4 Terminal Assignments

    16
  • 2.5 Terminal Descriptions

    24
• 3 Feature/Protocol Descriptions

  31
  • 3.1 Power-Up/Power-Down Sequencing

    31
    • 3.1.1 Power-Up Sequence

      32
    • 3.1.2 Power-Down Sequence

      33
  • 3.2 XIO2213B Reset Features

    34
  • 3.3 PCI Express (PCIe) Interface

    35
    • 3.3.1 External Reference Clock

      35
    • 3.3.2 Beacon and Wake

      35
    • 3.3.3 Initial Flow Control Credits

      35
    • 3.3.4 PCIe Message Transactions

      36
  • 3.4 PCI Interrupt Conversion to PCIe Messages

    37
  • 3.5 Two-Wire Serial-Bus Interface

    38
    • 3.5.1 Serial-Bus Interface Implementation

      38
    • 3.5.2 Serial-Bus Interface Protocol

      39
    • 3.5.3 Serial-Bus EEPROM Application

      41
    • 3.5.4 Accessing Serial-Bus Devices Through Softwaree

      43
  • 3.6 Advanced Error Reporting Registers

    43
  • 3.7 Data Error Forwarding Capability

    43
  • 3.8 General-Purpose I/O (GPIO) Interface

    44
  • 3.9 Set Slot Power Limit Functionality

    44
  • 3.10 PCIe and PCI Bus Power Management

    44
  • 3.11 1394b OHCI Controller Functionality

    46
    • 3.11.1 1394b OHCI Power Management

      46
    • 3.11.2 1394b OHCI and V AUX

      46
    • 3.11.3 1394b OHCI and Reset Options

      46
    • 3.11.4 1394b OHCI PCI Bus Master

      46
    • 3.11.5 1394b OHCI Subsystem Identification

      47
    • 3.11.6 1394b OHCI PME Support

      47
• 4 Classic PCI Configuration Space

  48
  • 4.1 Vendor ID Register

    49
  • 4.2 Device ID Register

    49
  • 4.3 Command Register

    49
  • 4.4 Status Register

    51
  • 4.5 Class Code and Revision ID Register

    52
  • 4.6 Cache Line Size Register

    52
  • 4.7 Primary Latency Timer Register

    52
  • 4.8 Header Type Register

    53
  • 4.9 BIST Register

    53
  • 4.10 Device Control Base Address Register

    53
  • 4.11 Scratchpad RAM Base Address

    54
  • 4.12 Primary Bus Number Register

    54
  • 4.13 Secondary Bus Number Register

    54
  • 4.14 Subordinate Bus Number Register

    55
  • 4.15 Secondary Latency Timer Register

    55
  • 4.16 I/O Base Register

    55
  • 4.17 I/O Limit Register

    56
  • 4.18 Secondary Status Register

    57
  • 4.19 Memory Base Register

    58
  • 4.20 Memory Limit Register

    58
  • 4.21 Prefetchable Memory Base Register

    59
  • 4.22 Prefetchable Memory Limit Register

    59
  • 4.23 Prefetchable Base Upper 32 Bits Register

    60
  • 4.24 Prefetchable Limit Upper 32 Bits Register

    60
  • 4.25 I/O Base Upper 16 Bits Register

    61
  • 4.26 I/O Limit Upper 16 Bits Register

    61
  • 4.27 Capabilities Pointer Register

    62
  • 4.28 Interrupt Line Register

    62
  • 4.29 Interrupt Pin Register

    62
  • 4.30  Bridge Control Register

    63
  • 4.31 PM Capability ID Register

    65
  • 4.32 Next Item Pointer Register

    65
  • 4.33 Power Management Capabilities Register

    66
  • 4.34 Power Management Control/Status Register

    67
  • 4.35 Power Management Bridge Support Extension Register

    68
  • 4.36 Power Management Data Register

    68
  • 4.37 MSI Capability ID Register

    68
  • 4.38 Next Item Pointer Register

    69
  • 4.39 MSI Message Control Register

    69
  • 4.40 MSI Message Lower Address Register

    70
  • 4.41 MSI Message Upper Address Register

    70
  • 4.42 MSI Message Data Register

    71
  • 4.43  SSID/SSVID Capability ID Register

    71
  • 4.44 Next Item Pointer Register

    71
  • 4.45 Subsystem Vendor ID Register

    72
  • 4.46 Subsystem ID Register

    72
  • 4.47 PCI Express Capability ID Register

    72
  • 4.48 Next Item Pointer Register

    72
  • 4.49 PCI Express Capabilities Register

    73
  • 4.50 Device Capabilities Register

    74
  • 4.51 Device Control Register

    75
  • 4.52 Device Status Register

    76
  • 4.53 Link Capabilities Register

    77
  • 4.54 Link Control Register

    78
  • 4.55 Link Status Register

    79
  • 4.56 Serial-Bus Data Register

    79
  • 4.57 Serial-Bus Word Address Register

    79
  • 4.58 Serial-Bus Slave Address Register

    80
  • 4.59 Serial-Bus Control and Status Register

    81
  • 4.60 GPIO Control Register

    82
  • 4.61 GPIO Data Register

    83
  • 4.62 Control and Diagnostic Register 0

    84
  • 4.63 Control and Diagnostic Register 1

    86
  • 4.64 PHY Control and Diagnostic Register 2

    87
  • 4.65 Subsystem Access Register

    88
  • 4.66 General Control Register

    88
  • 4.67 TI Proprietary Register

    91
  • 4.68 TI Proprietary Register

    91
  • 4.69 TI Proprietary Register

    91
  • 4.70 Arbiter Control Register

    92
  • 4.71 Arbiter Request Mask Register

    93
  • 4.72 Arbiter Time-Out Status Register

    94
  • 4.73 TI Proprietary Register

    95
  • 4.74 TI Proprietary Register

    95
  • 4.75 TI Proprietary Register

    95
• 5 PCIe Extended Configuration Space

  96
  • 5.1 Advanced Error Reporting Capability ID Register

    96
  • 5.2 Next Capability Offset/Capability Version Register

    97
  • 5.3 Uncorrectable Error Status Register

    97
  • 5.4 Uncorrectable Error Mask Register

    98
  • 5.5 Uncorrectable Error Severity Register

    99
  • 5.6 Correctable Error Status Register

    101
  • 5.7 Correctable Error Mask Register

    102
  • 5.8 Advanced Error Capabilities and Control Register

    103
  • 5.9 Header Log Register

    103
  • 5.10 Secondary Uncorrectable Error Status Register

    104
  • 5.11 Secondary Uncorrectable Error Mask Register

    105
  • 5.12 Secondary Uncorrectable Error Severity

    106
  • 5.13 Secondary Error Capabilities and Control Register

    107
  • 5.14 Secondary Header Log Register

    108
• 6 Memory-Mapped TI Proprietary Register Space

  109
  • 6.1 Device Control Map ID Register

    109
  • 6.2 Revision ID Register

    110
  • 6.3 GPIO Control Register

    110
  • 6.4 GPIO Data Register

    111
  • 6.5 Serial-Bus Data Register

    112
  • 6.6 Serial-Bus Word Address Register

    112
  • 6.7 Serial-Bus Slave Address Register

    112
  • 6.8 Serial-Bus Control and Status Register

    113
• 7 1394 OHCI PCI Configuration Space

  114
  • 7.1 Vendor ID Register

    115
  • 7.2 Device ID Register

    115
  • 7.3 Command Register

    116
  • 7.4 Status Register

    117
  • 7.5 Class Code and Revision ID Registers

    118
  • 7.6 Cache Line Size and Latency Timer Registers

    118
  • 7.7 Header Type and BIST Registers

    119
  • 7.8 OHCI Base Address Register

    119
  • 7.9 TI Extension Base Address Register

    120
  • 7.10 CIS Base Address Register

    120
  • 7.11 CIS Pointer Register

    121
  • 7.12 Subsystem Vendor ID and Subsystem ID Registers

    121
  • 7.13 Power Management Capabilities Pointer Register

    122
  • 7.14 Interrupt Line and Interrupt Pin Registers

    122
  • 7.15 Minimum Grant and Minimum Latency Registers

    123
  • 7.16 OHCI Control Register

    123
  • 7.17 Capability ID and Next Item Pointer Registers

    124
  • 7.18 Power Management Capabilities Register

    124
  • 7.19 Power Management Control and Status Register

    125
  • 7.20 Power Management Extension Registers

    125
  • 7.21 PCI Miscellaneous Configuration Register

    125
  • 7.22 Link Enhancement Control Register

    128
  • 7.23 Subsystem Access Register

    130
• 8 1394 OHCI Memory-Mapped Register Space

  131
  • 8.1 OHCI Version Register

    134
  • 8.2 GUID ROM Register

    135
  • 8.3 Asynchronous Transmit Retries Register

    136
  • 8.4 CSR Data Register

    136
  • 8.5 CSR Compare Register

    137
  • 8.6 CSR Control Register

    137
  • 8.7 Configuration ROM Header Register

    138
  • 8.8 Bus Identification Register

    138
  • 8.9 Bus Options Register

    139
  • 8.10 GUID High Register

    140
  • 8.11 GUID Low Register

    140
  • 8.12 Configuration ROM Mapping Register

    141
  • 8.13 Posted Write Address Low Register

    141
  • 8.14 Posted Write Address High Register

    142
  • 8.15 Vendor ID Register

    142
  • 8.16 Host Controller Control Register

    142
  • 8.17 Self-ID Buffer Pointer Register

    145
  • 8.18 Self-ID Count Register

    145
  • 8.19 Isochronous Receive Channel Mask High Register

    146
  • 8.20 Isochronous Receive Channel Mask Low Register

    148
  • 8.21 Interrupt Event Register

    148
  • 8.22 Interrupt Mask Register

    150
  • 8.23 Isochronous Transmit Interrupt Event Register

    152
  • 8.24 Isochronous Transmit Interrupt Mask Register

    153
  • 8.25 Isochronous Receive Interrupt Event Register

    153
  • 8.26 Isochronous Receive Interrupt Mask Register

    154
  • 8.27 Initial Bandwidth Available Register

    154
  • 8.28 Initial Channels Available High Register

    155
  • 8.29 Initial Channels Available Low Register

    155
  • 8.30 Fairness Control Register

    156
  • 8.31 Link Control Register

    157
  • 8.32 Node Identification Register

    158
  • 8.33 PHY Control Register

    159
  • 8.34 Isochronous Cycle Timer Register

    160
  • 8.35 Asynchronous Request Filter High Register

    160
  • 8.36 Asynchronous Request Filter Low Register

    163
  • 8.37 Physical Request Filter High Register

    163
  • 8.38 Physical Request Filter Low Register

    166
  • 8.39 Physical Upper Bound Register (Optional Register)

    166
  • 8.40 Asynchronous Context Control Register

    167
  • 8.41 Asynchronous Context Command Pointer Register

    168
  • 8.42 Isochronous Transmit Context Control Register

    169
  • 8.43 Isochronous Transmit Context Command Pointer Register

    170
  • 8.44 Isochronous Receive Context Control Register

    170
  • 8.45 Isochronous Receive Context Command Pointer Register

    172
  • 8.46 Isochronous Receive Context Match Register

    172
• 9 1394 OHCI Memory-Mapped TI Extension Register Space

  174
  • 9.1 Digital Video (DV) and MPEG2 Timestamp Enhancements

    174
  • 9.2 Isochronous Receive Digital Video Enhancements

    175
  • 9.3 Isochronous Receive Digital Video Enhancement Registers

    175
  • 9.4 Link Enhancement Control Registers

    176
  • 9.5 Timestamp Offset Registers

    178
• 10 Physical Layer (PHY) Section

  179
  • 10.1 PHY Section Register Configuration

    180
  • 10.2 PHY Section Application Information

    187
    • 10.2.1 Power Class Programming

      187
    • 10.2.2 Power-Up Reset

      188
    • 10.2.3 Crystal Oscillator Selection

      188
    • 10.2.4 Bus Reset

      189
• 11 Electrical Characteristics

  190
  • 11.1  Absolute Maximum Ratings

    190
  • 11.2  Recommended Operating Conditions

    190
  • 11.3  PCIe Differential Transmitter Output Ranges

    191
  • 11.4  PCIe Differential Receiver Input Ranges

    193
  • 11.5  PCIe Differential Reference Clock Input Ranges

    194
  • 11.6  Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)

    194
  • 11.7  Electrical Characteristics Over Recommended Operating Conditions (PHY Port Driver)

    195
  • 11.8 Switching Characteristics for PHY Port Driver

    195
  • 11.9  Electrical Characteristics Over Recommended Operating Conditions PHY Port Receiver

    196
  • 11.10  Jitter/Skew Characteristics for 1394a PHY Port Receiver

    196
  • 11.11  Operating, Timing, and Switching Characteristics of XI

    196
  • 11.12 Electrical Characteristics Over Recommended Operating Conditions (1394a Miscellaneous I/O)

    196
• 12 Glossary

  196