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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
8.30 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to
transmit multiple asynchronous requests during a fairness interval. See
transmit multiple asynchronous requests during a fairness interval. See
for a complete
description of the register contents.
OHCI register offset:
DCh
Register type:
Read only, Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 8-22. Fairness Control Registre Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31-8
RSVD
R
Reserved. Bits 31-8 return 00 0000h when read.
7-0
pri_req
RW
Priority requests. This field specifies the maximum number of priority arbitration requests for
asynchronous request packets that the link is permitted to make of the PHY during a fairness
interval. The default value for this field is 00h.
asynchronous request packets that the link is permitted to make of the PHY during a fairness
interval. The default value for this field is 00h.
156
1394 OHCI Memory-Mapped Register Space
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