Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 데이터 시트
제품 코드
XIO2213BEVM
TPAx+
TPBx+
TPAx-
TPBx-
56 W
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
11.7
Electrical Characteristics Over Recommended Operating Conditions (PHY Port
Driver)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1394a differential output voltage
56
172
265
V
OD
mV
1394b differential output voltage
700
Driver difference current (TPA+, TPA–, TPB+,
I
DIFF
Drivers enabled, speed signaling off
1.05
(1)
1.05
(1)
mA
TPB–)
I
SP20
Common-mode speed signaling current (TPB+,
S200 speed signaling enabled
4.84
(2)
2.53
(2)
mA
0
TPB–)
I
SP40
Common-mode speed signaling current (TPB+,
S400 speed signaling enabled
12.4
(2)
8.1
(2)
mA
0
TPB–)
V
OFF
Off-state differential voltage
Drivers disabled
20
mV
V
CM
1394b common-mode voltage
1.5
V
(1)
Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to algebraic sum of TPB+ and TPB– driver
currents.
currents.
(2)
Limits defined as absolute limit of each of TPB+ and TPB– driver currents.
Figure 11-1. Test Load Diagram
11.8 Switching Characteristics for PHY Port Driver
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Jitter, transmit
Between TPA and TPB
0.15
ns
Skew, transmit
Between TPA and TPB
0.1
ns
t
r
TP differential rise time, transmit
10% to 90%, at 1394 connector
0.5
1.2
ns
t
f
TP differential fall time, transmit
90% to 10%, at 1394 connector
0.5
1.2
ns
Setup time, CTL0, CTL1, D1-D7, LREQ until
50% to 50%
2.5
ns
t
su
PCLK - 1394a-2000
Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK
50% to 50%
0
ns
t
h
- 1394a-2000
Setup time, CTL0, CTL1, D1-D7, LREQ until
50% to 50%
2.5
ns
t
su
PCLK - 1394b
Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK
50% to 50%
1
ns
t
h
- 1394b
t
d
Delay time, PCLK until CTL0, CTL1, D1-D7, PINT
50% to 50%
0.5
7
ns
Copyright © 2008–2013, Texas Instruments Incorporated
Electrical Characteristics
195
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