Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 데이터 시트
제품 코드
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
Table 4-2. Command Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:11
RSVD
R
Reserved. Returns 00000b when read.
10
INT_DISABLE
R
INTx disable. This bit enables device specific interrupts. Since the bridge does not
generate any internal interrupts, this bit is read-only 0b.
generate any internal interrupts, this bit is read-only 0b.
9
FBB_ENB
R
Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;
therefore, this bit returns 0b when read.
therefore, this bit returns 0b when read.
8
SERR_ENB
RW
SERR enable. When this bit is set, the bridge can signal fatal and nonfatal errors on the
PCIe interface on behalf of SERR assertions detected on the PCI bus.
PCIe interface on behalf of SERR assertions detected on the PCI bus.
0 = Disable the reporting of nonfatal errors and fatal errors (default)
1 = Enable the reporting of nonfatal errors and fatal errors
1 = Enable the reporting of nonfatal errors and fatal errors
7
STEP_ENB
R
Address/data stepping control. The bridge does not support address/data stepping, and
this bit is hardwired to 0b.
this bit is hardwired to 0b.
6
PERR_ENB
RW
Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see
in response to a received poisoned TLP from PCIe. A received poisoned TLP is forwarded
with bad parity to conventional PCI, regardless of the setting of this bit.
with bad parity to conventional PCI, regardless of the setting of this bit.
0 = Disables the setting of the master data parity error bit (default)
1 = Enables the setting of the master data parity error bit
1 = Enables the setting of the master data parity error bit
5
VGA_ENB
R
VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore,
this bit returns 0b when read.
this bit returns 0b when read.
4
MWI_ENB
RW
Memory write and invalidate enable. When this bit is set, the bridge translates PCIe
memory write requests into memory write and invalidate transactions on the PCI interface.
memory write requests into memory write and invalidate transactions on the PCI interface.
0 = Disable the promotion to memory write and invalidate (default)
1 = Enable the promotion to memory write and invalidate
1 = Enable the promotion to memory write and invalidate
3
SPECIAL
R
Special cycle enable. The bridge does not respond to special cycle transactions; therefore,
this bit returns 0b when read.
this bit returns 0b when read.
2
MASTER_ENB
RW
Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on
the PCIe interface.
the PCIe interface.
0 = PCIe interface cannot initiate transactions. The bridge must disable the response
to memory and I/O transactions on the PCI interface (default).
1 = PCIe interface can initiate transactions. The bridge can forward memory and I/O
transactions from PCI secondary interface to the PCIe interface.
1
MEMORY_ENB
RW
Memory space enable. Setting this bit enables the bridge to respond to memory
transactions on the PCIe interface.
transactions on the PCIe interface.
0 = PCIe receiver cannot process downstream memory transactions and must
respond with an unsupported request (default)
1 = PCIe receiver can process downstream memory transactions. The bridge can
forward memory transactions to the PCI interface.
0
IO_ENB
RW
I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the
PCIe interface.
PCIe interface.
0 = PCIe receiver cannot process downstream I/O transactions and must respond
with an unsupported request (default)
1 = PCIe receiver can process downstream I/O transactions. The bridge can forward
I/O transactions to the PCI interface.
50
Classic PCI Configuration Space
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