Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 데이터 시트
제품 코드
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.14 Subordinate Bus Number Register
This read/write register specifies the bus number of the highest-number PCI bus segment that is
downstream of the bridge. Since the PCI bus is internal and only connects to the 1394a OHCI, this
register must always be equal to the secondary bus number register (offset 19h, see
downstream of the bridge. Since the PCI bus is internal and only connects to the 1394a OHCI, this
register must always be equal to the secondary bus number register (offset 19h, see
). The
bridge uses this register to determine how to respond to a type 1 configuration transaction.
PCI register offset:
1Ah
Register type:
Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
4.15 Secondary Latency Timer Register
This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock
cycles.
cycles.
PCI register offset:
1Bh
Register type:
Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
4.16 I/O Base Register
This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.
See
See
for a complete description of the register contents.
PCI register offset:
1Ch
Register type:
Read only, Read/Write
Default value:
01h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
1
Table 4-7. I/O Base Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:4
IOBASE
3:0
IOTYPE
R
I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
Copyright © 2008–2013, Texas Instruments Incorporated
Classic PCI Configuration Space
55
Product Folder Links: