Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 데이터 시트
제품 코드
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.55 Link Status Register
The link status register indicates the current state of the PCIe link. See
for a complete
description of the register contents.
PCI register offset:
A2h
Register type:
Read only
Default value:
X011h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
x
0
0
0
0
0
0
0
1
0
0
0
1
Table 4-31. Link Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:13
RSVD
R
Reserved. Returns 000b when read.
12
SCC
R
Slot clock configuration. This bit indicates that the bridge uses the same physical reference
clock that the platform provides on the connector. If the bridge uses an independent clock
irrespective of the presence of a reference on the connector, this bit must be cleared.
clock that the platform provides on the connector. If the bridge uses an independent clock
irrespective of the presence of a reference on the connector, this bit must be cleared.
0 = Independent 125-MHz reference clock is used.
1 = Common 100-MHz reference clock is used.
1 = Common 100-MHz reference clock is used.
11
LT
R
Link training. This bit has no function and is read-only 0b.
10
TE
R
Retrain link. This bit has no function and is read-only 0b.
9:4
NLW
R
Negotiated link width. This field is read-only 00 0001b indicating the lane width is 1×.
3:0
LS
R
Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.
4.56 Serial-Bus Data Register
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register (offset B2h, see
register prior to writing the serial-bus slave address register (offset B2h, see
) that initiates the
bus cycle. When reading data from the serial bus, this register contains the data read after bit 5
(REQBUSY) of the serial-bus control and status register (offset B3h, see
(REQBUSY) of the serial-bus control and status register (offset B3h, see
) is cleared. This
register shall only be reset by FRST.
PCI register offset:
B0h
Register type:
Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
4.57 Serial-Bus Word Address Register
The value written to the serial-bus word address register represents the word address of the byte being
read from or written to the serial-bus device. The word address is loaded into this register prior to writing
the serial-bus slave address register (offset B2h, see
read from or written to the serial-bus device. The word address is loaded into this register prior to writing
the serial-bus slave address register (offset B2h, see
) that initiates the bus cycle. This
register shall only be reset by FRST.
PCI register offset:
B1h
Register type:
Read/Write
Default value:
00h
Copyright © 2008–2013, Texas Instruments Incorporated
Classic PCI Configuration Space
79
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