Texas Instruments TLK10002SMAEVM Evaluation Module TLK10002SMAEVM TLK10002SMAEVM 데이터 시트
제품 코드
TLK10002SMAEVM
O
N
N
X
C
F
3
2
P
F
G48
JMP7
P3
T
L
K
1
0
0
0
2
E
V
M
F
P
G
A
D
A
U
G
H
T
E
R
B
O
A
R
D
R
E
V
N
A
6
5
2
2
8
5
1
P1
P2
+5V
+5V
P
L
U
G
+
5
V
B
J
C
5
4
C
5
5
C
5
6
C47
R62
R65
R64
R60
R64
R60
C44
C45
R54
R52
R46
R46
R49
C33
C30
C29
Q
1
7
U9
U10
Q
1
9
1P2V GTP
G
N
D
E
N
L3
C57
C60
J
M
P
3
JMP31
G
N
D
E
N
J
M
P
6
1P2V REG
L4
C61
C64
JMP32
C
3
8
C
3
9
R
5
8
R
6
3
R
6
6
JMP17
3
P
3
V
R
E
G
U11
C
4
6
R61
J
M
P
5
G
N
D
E
N
Q
1
8
U8
2
P
5
V
R
E
G
Q
1
6
R48
J
M
P
2
C
3
2
R
5
3
R
5
1
R
4
4
C
2
4
C
2
3
G
N
D
E
N
G
N
D
E
N
1
P
8
V
R
E
G
L1
C48
C51
J
M
P
3
0
C
1
7
C
1
8
R
4
2
R
5
0
R
5
6
C
3
1
Q
1
5
R47
J
M
P
1
U7
J
M
P
1
6
G
N
D
C
L
K
1
JMP4
R
5
5
1
P
8
V
D
4
6
D
4
7
V
C
C
O
_
1
P
8
V
U
3
7
C243
U36
U39
U42
U30
U33
C242
C241
C245
C244
U
4
0
U
4
3
U
3
1
U
3
4
D
4
5
D
4
4
D
4
3
D
4
2
D
5
1
D
5
0
D
4
9
D
4
8
2
P
5
V
V
C
C
A
U
X
_
2
P
5
V
3
P
3
V
V
C
C
C
L
K
_
3
P
3
V
1
P
2
V
V
C
C
IN
T
_
1
P
2
V
1
P
2
V
_
G
T
P
V
C
C
M
G
T
_
1
P
2
V
GND
J
M
P
1
4
J
M
P
1
3
CHB_CLKN
CHB_CLKP
IO_SIGNALS
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
J
M
P
2
2
IO
S
IG
N
A
L
S
G
N
D
C
L
K
1
F
P
G
A
R
E
-P
R
O
G
R
A
M
G
C
L
K
2
5
G
C
L
K
2
7
G
C
L
K
1
2
G
C
L
K
1
7
J11
J10
J9
J7
SW5
U
S
B
USB
J2
R
E
S
E
T
SW6
MAIN RESET
PB3 RESET
PB4 RESET
PB2 RESET
PB1 RESET
SW1
SW2
SW3
SW4
SW8
MDIO RESET
G
C
L
K
1
4
SW9
J8
CHA_CLKp
CHA_CLKn
JM
P
2
1
JMP15
JMP9
JTAG
U44
JM
P
2
1
J4
J6
SW7
GND
GND
SDA
I2C
1
G
P
IO
_
1
G
P
IO
_
2
G
P
IO
_
3
G
P
IO
_
4
G
P
IO
_
5
JMP33
C67
C65
L5
JMP11
C21
C213
C217
C213
C217
SMA
CHB_CLK_SEL
TLK CLK
L6
C69
D21
C72
D18
J
M
P
3
4
R70
PROG_B_RST
R67
R74
R80
R81
R81
R75
PROG_B_/RST
J
M
P
8
U13
C200
R78
JMP23
R267
R266
R265
R243
R
3
7
7
HSWAPEN
J
M
P
3
6
J
M
P
1
8
R
2
6
4
GND
C212
C211
C218
TLK CLK
CHA_CLK_SEL
SMA
JMP10
2
5
5
3
1
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
C154
C160
C156
C148
C173
C164
C157
C149
C259
R88
R89
R86
R84
R84
R83
R385
R386
R386
R381
R87
R85
R82
R85
R82
C
2
4
6
1
3
5
C
2
3
5
C
2
4
7
R77
R91
R91
C256
C255
C255
A
C
E
G
2 4 6
B
D
F
H
H
R76
R79
R79
JMP29
C12
C11
C11
C10
R
3
0
R
4
0
R
3
1
R
3
2
R25 R34
C8
R
3
3
R
2
6
R
1
0
C2
C5
R8
R5
U5
C1
R38
R39
R9
R6
R6
R3
D
1
4
U
S
B
_
R
S
T
R
2
U
6
D13
D
1
6
D
1
5
U
S
B
_
O
N
L
IN
E
U
S
B
_
S
U
S
P
C4
R
3
5
1
R
2
0
1
R
2
0
2
R
3
5
2
U
S
B
_
/R
S
T
R1
C9
R
1
3
4
R
2
1
4
R
2
1
3
C236
C261
R
2
1
2
C
2
3
3
Q32
Q31
2
P
5
V
M
D
IO
3
P
3
V
JMP20
R
1
9
9
R197
R
2
0
0
R198 R206 R205
JMP28
JMP19
M
D
C
_
C
O
N
M
D
IO
_
C
O
N
M
D
C
M
D
IO
R
1
3
2
C
2
4
0
JMP12
U16
D22 D23
R
1
3
1
R
S
T
R
S
T
L
E
D
9
D
9
L
E
D
1
0
R
2
2
6
D
1
0
R
2
2
4
L
S
_
O
K
_
IN
_
B
D
2
6
R
1
7
3
L
E
D
8
D
8
R
2
2
8
L
S
_
O
K
_
O
U
T
_
B
R
2
8
9
U27
JMP27
D39 D40
R
2
9
5
R
2
8
7
R
S
T
R
S
T
P
B
3
R
S
T
R
S
T
P
B
4
R
S
T
R
S
T
P
B
2
R
S
T
R
S
T
P
B
1
D
2
7
R
1
7
4
R
2
4
2
L
E
D
1
D
1
L
E
D
1
2
D
1
2
R
2
2
0
L
E
D
1
1
D
1
1
R
2
2
2
L
E
D
2
D
2
R
2
4
0
R
2
9
2
R
2
8
5
L
S
_
O
K
_
O
U
T
_
A
D
2
5
R
1
7
2
L
E
D
3
D
3
R
2
3
8
L
E
D
4
D
4
R
2
3
6
L
S
_
O
K
_
IN
_
A
D
2
4
R
1
7
1
L
E
D
7
R
2
7
6
R
2
7
1
R
2
7
8
R
2
6
9
D
7
R
2
3
0
L
E
D
6
R
2
3
4
D
5
L
E
D
6
D
6
R
2
3
2
D
O
N
E
R
6
9
D19
D20
D20
JMP24
D34 D36
U21
JMP25
D35 D37
JMP26
U23
D38 D41
U25
C
2
3
9
R
2
8
8
C
2
3
8
R
2
7
3
C
2
3
7
R
2
7
2
D
5
2
5
V
R
3
8
3
R
6
8
Q
2
1
/I
N
IT
_
B
Q
3
4
D
5
3
/B
U
S
Y
D28
R175
LOSA
LOSB
LOSA
LOSB
D29
R176
TEST_PASS_A
TST_PASS_A
D30
R177
TEST_PASS_B
D31
R178
TST_PASS_B
JMP35
R191
D33
D32
RST
RST
MDIO
R188
R189
S
U
S
P
E
N
D
E
D
D
5
4
R
3
9
8
U18
C234
XIL
IN
X
SP
AR
TA
N-6
XC
6S
LX
75
T
C
2
0
1
C
2
0
3
C
2
0
7
C
2
0
2
PDTRXA_N
PRBSEN
TEST_EN_A
TEST_EN_B
G
N
D
LANE2_4_SELECT_A
LANE2_4_SELECT_B
LOOPBACK_A
LOOPBACK_B
SCL
V
C
C
A
U
X
_
2
P
5
V
T
M
S
T
C
K
T
D
O
T
D
I
P
R
T
A
D
0
P
R
T
A
D
1
P
R
T
A
D
2
P
R
T
A
D
3
P
R
T
A
D
4
2
3
2
1
1
9
C
2
3
0
C
2
2
8
C
2
2
2
C
2
2
4
C
2
2
0
C
2
1
5
C
2
0
6
C
2
0
5
9
7
U14
J3
J5
C
23
2 C22
5
U1
C
2
5
1
R
3
6
5
R
3
6
2
R
3
6
3
R
3
6
6
R
3
6
1
R
3
6
4
C
2
5
3
C
2
2
7
C
2
2
9
C
2
2
3
C
2
2
1
C
2
1
6
C
2
0
4
C
2
1
9
C
2
0
8
U15
C
22
6
C
23
1
Test and Setup Configurations
Figure 3. TLK10002EVM FPGA Daughterboard
11
SLLU148
–
May 2011
TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated