Texas Instruments TLK10002SMAEVM Evaluation Module TLK10002SMAEVM TLK10002SMAEVM 데이터 시트
제품 코드
TLK10002SMAEVM
Control and Output Status Signals
5
Control and Output Status Signals
All of the external control and status pins on the TLK10002EVM have been consolidated to a single
location on the board and broken out into several header blocks for easier reference. LEDs have been
added to the LOSA, LOSB, PRBS_PASS, and PLL_LOCK of the CDCE72010 jitter cleaner lines in
addition to the headers for scope probes to allow easy monitoring of the high/low value on the line. The
LED is ON when the line is a logic high, and the LED is OFF when the line is a logic low. If the line is
toggling, a dimming of the LED may be observed as the LED is pulsing on and off relative to the activity
on the line.
location on the board and broken out into several header blocks for easier reference. LEDs have been
added to the LOSA, LOSB, PRBS_PASS, and PLL_LOCK of the CDCE72010 jitter cleaner lines in
addition to the headers for scope probes to allow easy monitoring of the high/low value on the line. The
LED is ON when the line is a logic high, and the LED is OFF when the line is a logic low. If the line is
toggling, a dimming of the LED may be observed as the LED is pulsing on and off relative to the activity
on the line.
All status pins and external control pins of the TLK10002 and the CDCE72010 can also be monitored or
set high/low through the GUI. The preferred method of setting these control pins is through the GUI via the
TCA6424 I2C-to-GPIO IC located on the board. If shunts are placed on the header for a particular control
pin, the signal is physically tied low and software control is not possible. Mixed use of the hardware and
software setting of various control pins is discouraged.
set high/low through the GUI. The preferred method of setting these control pins is through the GUI via the
TCA6424 I2C-to-GPIO IC located on the board. If shunts are placed on the header for a particular control
pin, the signal is physically tied low and software control is not possible. Mixed use of the hardware and
software setting of various control pins is discouraged.
The I2C-based software control of the TLK10002 control pins can be disabled by placing a shunt on
JMP44, which disables the level shifter attached to the signals by setting the enable pins low. This allows
the onboard pullup resistors or shunts to ground on the header pins to set the high/low status of the
control pins. If external control is desired, the Software Control radio button on the GUI front panel must
be de-selected as well to disable the software portion of the interface.
JMP44, which disables the level shifter attached to the signals by setting the enable pins low. This allows
the onboard pullup resistors or shunts to ground on the header pins to set the high/low status of the
control pins. If external control is desired, the Software Control radio button on the GUI front panel must
be de-selected as well to disable the software portion of the interface.
See the TLK10002 data sheet for a detailed description of the control signals.
6
MDIO
The TLK10002 supports the Management Data Input/Output (MDIO) interface as defined in Clause 22 of
the IEEE 802.3 Ethernet Specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK10002 is possible without the use of this interface, although some
additional features are accessible only through the MDIO interface.
the IEEE 802.3 Ethernet Specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK10002 is possible without the use of this interface, although some
additional features are accessible only through the MDIO interface.
The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference
(MDC). The port address is determined by control pins PRTAD[4:0] as described in Table 1 of the
TLK10002 data sheet.
(MDC). The port address is determined by control pins PRTAD[4:0] as described in Table 1 of the
TLK10002 data sheet.
In Clause 22, the top four control pins PRTAD[4:1] determine the device port address. In this mode, the
two individual channels in TLK10002 are classified as two different ports. So, any PRTAD[4:1] value has
two ports per TLK10002. The TLK10002 responds if the four MSBs of the PHY address field on MDIO
protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which
channel/port within the TLK10002 to respond to.
two individual channels in TLK10002 are classified as two different ports. So, any PRTAD[4:1] value has
two ports per TLK10002. The TLK10002 responds if the four MSBs of the PHY address field on MDIO
protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which
channel/port within the TLK10002 to respond to.
If PA[0] = 1
’
b0, TLK10002
’
s channel A responds.
If PA[0] = 1
’
b1, TLK10002
’
s channel B responds.
Write transactions that address an invalid register or read only registers are ignored. Read transactions of
invalid registers return a 0.
invalid registers return a 0.
The TLK10002 requires either 1.5-V or 1.8-V I/O levels on the MDIO/MDC signals. Therefore, a
bidirectional level shifter has been provided on board that level shift the 3.3-V MDIO and MDC signals to
the appropriate 1.5-V/8-V levels. If a different MDIO controller is used that already has 1.5-V or 1.8-V
signal levels, resistors R308, R309, R296, and R297 must be removed, thus disconnecting the level
shifter. Resistors R293 and R295 can be installed which connect the TLK10002 MDIO and MDC signal
pins directly to the pins of JMP50. A third option of using NFETs as level shifters has also been provided.
Removing resistors R308, R309, R296, and R297, as well R293 and R295 if they were installed and
installing an appropriate NFET such as Fairchild
bidirectional level shifter has been provided on board that level shift the 3.3-V MDIO and MDC signals to
the appropriate 1.5-V/8-V levels. If a different MDIO controller is used that already has 1.5-V or 1.8-V
signal levels, resistors R308, R309, R296, and R297 must be removed, thus disconnecting the level
shifter. Resistors R293 and R295 can be installed which connect the TLK10002 MDIO and MDC signal
pins directly to the pins of JMP50. A third option of using NFETs as level shifters has also been provided.
Removing resistors R308, R309, R296, and R297, as well R293 and R295 if they were installed and
installing an appropriate NFET such as Fairchild
’
s FDV301N allows for this third option of level shifting to
be evaluated.
The onboard TUSB3210 microcontroller is the preferred method of controlling the TLK10002 register stack
and is the only way to interface the GUI with the board.
and is the only way to interface the GUI with the board.
7
SLLU148
–
May 2011
TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated