Texas Instruments Evaluation Module for TPS2540 USB Charging Port Power Switch & Controller TPS2540EVM-623 TPS2540EVM-623 데이터 시트
제품 코드
TPS2540EVM-623
General Configuration and Description
3
General Configuration and Description
3.1
Physical Access
lists the TPS2540EVM-623 connector functionality,
describes the test point availability
and Table 3 describes the jumper functionality.
Table 1. Connector Functionality
Connector
Label
Description
J1
AUX
Auxiliary high current input connector.
J2
USB INPUT
USB input port.
J3A
(UPPER)
Primary charging port (with data).
J3B
(LOWER)
Auxiliary charging port (no data).
D1 (RED)
FAULT
Fault LED
D2 (GREEN)
VOUT-ON
USB Output Powered
S1
S1
Mode switch used in conjunction with
Table 2. Test Points
Test Point
Color
Label
Description
TP3
RED
IN
Power bus input.
TP4
RED
VOUT
Power bus output.
TP5
SM
TP3
Power bus GND.
TP1
WHT
DP-OUT
Data+ out
TP2
WHT
DM-OUT
Data- out
TP6
SM
TP5
Power bus GND
TP7
(1)
ORG
DP-IN
Data+ in
TP8
(1)
ORG
DM-IN
Data- in
(1)
TP7 and TP8 are isolated from U1 DP_IN (U1-11) and DM_IN (U1-10) respectively with 1M
Ω
resistors to minimize degradation
of high speed signal quality. Static voltage measurements of U1 DP_IN or DM_IN through TP7 and TP8 will be affected by the
loading of the test instrument and 1M
loading of the test instrument and 1M
Ω
resistors.
Table 3. Jumpers
Jumper
Label
Description
JP1
VIN
Power bus input. Install shunt to allow charger source to power TPS2540/1 and downstream circuitry.
JP2
VOUT
Power bus output. Install shunt to allow charger source to power downstream devices.
JP3
CTL3
CTL3. See MODE truth table
JP4
CTL2
CTL2. See MODE truth table
JP5
CTL1
CTL1. See MODE truth table
JP6
EN
TPS2540/40A/41/41A Enable select. Install shunt to disable TPS2540/40A/41/41A (also discharges the output capacitor for
TPS2541/41A).
TPS2541/41A).
JP7
ILIM
ILIM select. Install shunt to select ILIM0 (2.43A typical ILIM). Remove shunt to select ILIM1 (1.21A typical ILIM).
The CTL pins configure the device mode. Setting S1 to the CDP position (open) is equivalent to setting
the CTL pins to the state in the last row of
the CTL pins to the state in the last row of
. Setting S1 to the DIS/SDP/DCP position allows the
remaining rows to be configured.
Table 4. TPS2540/40A Mode Truth Table
CTL1 (JP5)
CTL2 (JP4)
CTL3 (JP3)
Mode
0
0
0
OUT discharge, power switch OFF
0
X
1
Dedicated Charging Port, Auto-detect
X
1
0
Standard Downstream Port, USB 2.0 Mode
1
0
0
Dedicated Charging Port, BC Specification 1.1 only
4
TPS2540EVM-623: Evaluation Module for TPS2540/40A and TPS2541/41A
SLVU401B
–
September 2010
–
Revised August 2011
Copyright
©
2010
–
2011, Texas Instruments Incorporated