Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L 데이터 시트
제품 코드
TMDXEVMWIFI1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.27 Video Port Interface (VPIF)
The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:
•
Up to 2 Video Capture Channels (Channel 0 and Channel 1)
–
–
Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
–
Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
–
Single Raw Video (8-/10-/12-bit)
•
Up to 2 Video Display Channels (Channel 2 and Channel 3)
–
–
Two 8-bit SD Video Display with embedded timing codes (BT.656)
–
Single 16-bit HD Video Display with embedded timing codes (BT.1120)
The VPIF capture channel input data format is selectable based on the settings of the specific Channel
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings
of the Channel 0 Control Register.
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings
of the Channel 0 Control Register.
6.27.1 VPIF Register Descriptions
shows the VPIF registers.
Table 6-114. Video Port Interface (VPIF) Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 7000
PID
Peripheral identification register
0x01E1 7004
CH0_CTRL
Channel 0 control register
0x01E1 7008
CH1_CTRL
Channel 1 control register
0x01E1 700C
CH2_CTRL
Channel 2 control register
0x01E1 7010
CH3_CTRL
Channel 3 control register
0x01E1 7014 - 0x01E1 701F
-
Reserved
0x01E1 7020
INTEN
Interrupt enable
0x01E1 7024
INTENSET
Interrupt enable set
0x01E1 7028
INTENCLR
Interrupt enable clear
0x01E1 702C
INTSTAT
Interrupt status
0x01E1 7030
INTSTATCLR
Interrupt status clear
0x01E1 7034
EMU_CTRL
Emulation control
0x01E1 7038
DMA_SIZE
DMA size control
0x01E1 703C - 0x01E1 703F
-
Reserved
CAPTURE CHANNEL 0 REGISTERS
0x01E1 7040
CH0_TY_STRTADR
Channel 0 Top Field luma buffer start address
0x01E1 7044
CH0_BY_STRTADR
Channel 0 Bottom Field luma buffer start address
0x01E1 7048
CH0_TC_STRTADR
Channel 0 Top Field chroma buffer start address
0x01E1 704C
CH0_BC_STRTADR
Channel 0 Bottom Field chroma buffer start address
0x01E1 7050
CH0_THA_STRTADR
Channel 0 Top Field horizontal ancillary data buffer start address
0x01E1 7054
CH0_BHA_STRTADR
Channel 0 Bottom Field horizontal ancillary data buffer start address
0x01E1 7058
CH0_TVA_STRTADR
Channel 0 Top Field vertical ancillary data buffer start address
0x01E1 705C
CH0_BVA_STRTADR
Channel 0 Bottom Field vertical ancillary data buffer start address
0x01E1 7060
CH0_SUBPIC_CFG
Channel 0 sub-picture configuration
0x01E1 7064
CH0_IMG_ADD_OFST
Channel 0 image data address offset
0x01E1 7068
CH0_HA_ADD_OFST
Channel 0 horizontal ancillary data address offset
0x01E1 706C
CH0_HSIZE_CFG
Channel 0 horizontal data size configuration
0x01E1 7070
CH0_VSIZE_CFG0
Channel 0 vertical data size configuration (0)
0x01E1 7074
CH0_VSIZE_CFG1
Channel 0 vertical data size configuration (1)
0x01E1 7078
CH0_VSIZE_CFG2
Channel 0 vertical data size configuration (2)
0x01E1 707C
CH0_VSIZE
Channel 0 vertical image size
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Peripheral Information and Electrical Specifications
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