Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L 데이터 시트
제품 코드
TMDXEVMWIFI1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-114. Video Port Interface (VPIF) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
CAPTURE CHANNEL 1 REGISTERS
0x01E1 7080
CH1_TY_STRTADR
Channel 1 Top Field luma buffer start address
0x01E1 7084
CH1_BY_STRTADR
Channel 1 Bottom Field luma buffer start address
0x01E1 7088
CH1_TC_STRTADR
Channel 1 Top Field chroma buffer start address
0x01E1 708C
CH1_BC_STRTADR
Channel 1 Bottom Field chroma buffer start address
0x01E1 7090
CH1_THA_STRTADR
Channel 1 Top Field horizontal ancillary data buffer start address
0x01E1 7094
CH1_BHA_STRTADR
Channel 1 Bottom Field horizontal ancillary data buffer start address
0x01E1 7098
CH1_TVA_STRTADR
Channel 1 Top Field vertical ancillary data buffer start address
0x01E1 709C
CH1_BVA_STRTADR
Channel 1 Bottom Field vertical ancillary data buffer start address
0x01E1 70A0
CH1_SUBPIC_CFG
Channel 1 sub-picture configuration
0x01E1 70A4
CH1_IMG_ADD_OFST
Channel 1 image data address offset
0x01E1 70A8
CH1_HA_ADD_OFST
Channel 1 horizontal ancillary data address offset
0x01E1 70AC
CH1_HSIZE_CFG
Channel 1 horizontal data size configuration
0x01E1 70B0
CH1_VSIZE_CFG0
Channel 1 vertical data size configuration (0)
0x01E1 70B4
CH1_VSIZE_CFG1
Channel 1 vertical data size configuration (1)
0x01E1 70B8
CH1_VSIZE_CFG2
Channel 1 vertical data size configuration (2)
0x01E1 70BC
CH1_VSIZE
Channel 1 vertical image size
DISPLAY CHANNEL 2 REGISTERS
0x01E1 70C0
CH2_TY_STRTADR
Channel 2 Top Field luma buffer start address
0x01E1 70C4
CH2_BY_STRTADR
Channel 2 Bottom Field luma buffer start address
0x01E1 70C8
CH2_TC_STRTADR
Channel 2 Top Field chroma buffer start address
0x01E1 70CC
CH2_BC_STRTADR
Channel 2 Bottom Field chroma buffer start address
0x01E1 70D0
CH2_THA_STRTADR
Channel 2 Top Field horizontal ancillary data buffer start address
0x01E1 70D4
CH2_BHA_STRTADR
Channel 2 Bottom Field horizontal ancillary data buffer start address
0x01E1 70D8
CH2_TVA_STRTADR
Channel 2 Top Field vertical ancillary data buffer start address
0x01E1 70DC
CH2_BVA_STRTADR
Channel 2 Bottom Field vertical ancillary data buffer start address
0x01E1 70E0
CH2_SUBPIC_CFG
Channel 2 sub-picture configuration
0x01E1 70E4
CH2_IMG_ADD_OFST
Channel 2 image data address offset
0x01E1 70E8
CH2_HA_ADD_OFST
Channel 2 horizontal ancillary data address offset
0x01E1 70EC
CH2_HSIZE_CFG
Channel 2 horizontal data size configuration
0x01E1 70F0
CH2_VSIZE_CFG0
Channel 2 vertical data size configuration (0)
0x01E1 70F4
CH2_VSIZE_CFG1
Channel 2 vertical data size configuration (1)
0x01E1 70F8
CH2_VSIZE_CFG2
Channel 2 vertical data size configuration (2)
0x01E1 70FC
CH2_VSIZE
Channel 2 vertical image size
0x01E1 7100
CH2_THA_STRTPOS
Channel 2 Top Field horizontal ancillary data insertion start position
0x01E1 7104
CH2_THA_SIZE
Channel 2 Top Field horizontal ancillary data size
0x01E1 7108
CH2_BHA_STRTPOS
Channel 2 Bottom Field horizontal ancillary data insertion start position
0x01E1 710C
CH2_BHA_SIZE
Channel 2 Bottom Field horizontal ancillary data size
0x01E1 7110
CH2_TVA_STRTPOS
Channel 2 Top Field vertical ancillary data insertion start position
0x01E1 7114
CH2_TVA_SIZE
Channel 2 Top Field vertical ancillary data size
0x01E1 7118
CH2_BVA_STRTPOS
Channel 2 Bottom Field vertical ancillary data insertion start position
0x01E1 711C
CH2_BVA_SIZE
Channel 2 Bottom Field vertical ancillary data size
0x01E1 7120 - 0x01E1 713F
-
Reserved
DISPLAY CHANNEL 3 REGISTERS
0x01E1 7140
CH3_TY_STRTADR
Channel 3 Field 0 luma buffer start address
0x01E1 7144
CH3_BY_STRTADR
Channel 3 Field 1 luma buffer start address
0x01E1 7148
CH3_TC_STRTADR
Channel 3 Field 0 chroma buffer start address
224
Peripheral Information and Electrical Specifications
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