Texas Instruments PCM5142 Evaluation Module PCM5142EVM-U PCM5142EVM-U 데이터 시트
제품 코드
PCM5142EVM-U
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
System Clock PLL Mode
The system clock PLL mode allows designers to use a simple 3-wire I
2
S audio source when driving the DAC.
The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high
frequency electromagnetic interference.
frequency electromagnetic interference.
In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly
while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically
generating an internal SCK from the BCK reference. The PCM514x disables the internal PLL when an external
SCK is supplied; specific BCK rates are required to generate an appropriate master clock.
while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically
generating an internal SCK from the BCK reference. The PCM514x disables the internal PLL when an external
SCK is supplied; specific BCK rates are required to generate an appropriate master clock.
describes the
minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.
In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied; specific BCK rates are
required to generate an appropriate master clock.
required to generate an appropriate master clock.
lists the minimum and maximum BCK per LRCK for
the Integrated PLL to automatically generate an internal SCK.
In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See
for more information.
Table 8. BCK Rates (MHz) by LRCK Sample Rate for
PCM514x PLL Operation
BCK (f
S
)
Sample f (kHz)
32
64
8
-
-
16
-
1.024
32
1.024
2.048
44.1
1.4112
2.8224
48
1.536
3.072
96
3.072
6.144
192
6.144
12.288
384
12.288
24.576
Clock Generation and PLL
The PCM514x supports a wide range of options to generate the required clocks for the DAC section as well as
interface and other control blocks as shown in
interface and other control blocks as shown in
The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK.
The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page
0, Register 13, D(6:4). The PLL reference clock can then be routed through highly-flexible clock dividers shown
in
0, Register 13, D(6:4). The PLL reference clock can then be routed through highly-flexible clock dividers shown
in
to generate the various clocks required for the DAC, Negative Charge Pump (NCP), Internal
modulator and miniDSP sections. The PCM514x provides several programmable clock dividers to achieve a
variety of sampling rates for the DAC and clocks for the NCP, OSR, and the miniDSP. OSRCK for OSR must be
set at 16f
variety of sampling rates for the DAC and clocks for the NCP, OSR, and the miniDSP. OSRCK for OSR must be
set at 16f
S
frequency by DOSR on Page0, Register 30, D(6:0).
If PLL functionality isn’t required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an
external SCK is required.
external SCK is required.
Table 9. PLL Configuration Registers
Clock multiplexer
Function
Bits
SRCREF
PLL Reference
Page 0, Register 13, D(6:4)
Divider
Function
Bits
DDSP
miniDSP clock divider
Page 0, Register 27, D(6:0)
DDAC
DAC clock divider
Page 0, Register 28, D(6:0)
DNCP
NCP clock divider
Page 0, Register 29, D(6:0)
DOSR
OSR clock divider
Page 0, Register 30, D(6:0)
DBCK
External BCK Div
Page 0, Register 32, D(6:0)
Copyright © 2012, Texas Instruments Incorporated
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