Texas Instruments PCM5142 Evaluation Module PCM5142EVM-U PCM5142EVM-U 데이터 시트
제품 코드
PCM5142EVM-U
SCK
BCK
OSC
GPIO
SRCREF
PLL
K * R /
P
K = J.D
J = 1,2,3,
J = 1,2,3,
..,62,63
D = 0000, 0001,
., 9998, 9999
R = 1,2,3,4,
.,15, 16
P = 1,2,
.,127,128
PLLCK
MCK
SCK
BCK
OSCCK
PLLCK
SRCD AC
Q=1,2,3,
..,127,128
GPIO
DIV
Q
DSPCK
Q=1,2,3,
..,127,128
DIV
Q
SCK
PLLEN
Q=1,2,3,
..,127,128
DIV
Q
DACCK
CPCK
Q=1,2,3,
..,127,128
DIV
Q
OSRCK
DIV
Q
OFSCCK
OSCCK
Q=1,2,3,
..,127,128
DIV
Q
BCKO
SCK
Q=1,2,3,
..,127,128
DIV
Q
LRCK O
Q=1,2,3,
..,127,128
PLLCKIN
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
Table 9. PLL Configuration Registers (continued)
DLRK
External LRCK Div
Page 0, Register 33, D(7:0)
Figure 26. PLL Clock Source and Clock Distribution
24
Copyright © 2012, Texas Instruments Incorporated
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