Microchip Technology MA180023 데이터 시트
PIC18F46J11 FAMILY
DS39932D-page 56
2011 Microchip Technology Inc.
4.6.3
DEEP SLEEP WAKE-UP SOURCES
While in Deep Sleep mode, the device can be awakened
by a MCLR, POR, RTCC, INT0 I/O pin interrupt,
DSWDT or ULPWU event. After waking, the device per-
forms a POR. When the device is released from Reset,
code execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the DS
bit (WDTCON<3>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DS bit must be
manually cleared by the software.
The software can determine the wake event source by
reading the DSWAKEH and DSWAKEL registers.
When the application firmware is done using the
DSWAKEH and DSWAKEL status registers, individual
bits do not need to be manually cleared before entering
Deep Sleep again. When entering Deep Sleep mode,
these registers are automatically cleared.
by a MCLR, POR, RTCC, INT0 I/O pin interrupt,
DSWDT or ULPWU event. After waking, the device per-
forms a POR. When the device is released from Reset,
code execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the DS
bit (WDTCON<3>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DS bit must be
manually cleared by the software.
The software can determine the wake event source by
reading the DSWAKEH and DSWAKEL registers.
When the application firmware is done using the
DSWAKEH and DSWAKEL status registers, individual
bits do not need to be manually cleared before entering
Deep Sleep again. When entering Deep Sleep mode,
these registers are automatically cleared.
4.6.3.1
Wake-up Event Considerations
Deep Sleep wake-up events are only monitored while
the processor is fully in Deep Sleep mode. If a wake-up
event occurs before Deep Sleep mode is entered, the
event status will not be reflected in the DSWAKE regis-
ters. If the wake-up source asserts prior to entering
Deep Sleep, the CPU may go to the interrupt vector (if
the wake source has an interrupt bit and the interrupt is
fully enabled), and may abort the Deep Sleep entry
sequence by executing past the SLEEP instruction. In
this case, a wake-up event handler should be placed
after the SLEEP instruction to process the event and
re-attempt entry into Deep Sleep if desired.
When the device is in Deep Sleep with more than one
wake-up source simultaneously enabled, only the first
wake-up source to assert will be detected and logged
in the DSWAKEH/DSWAKEL status registers.
the processor is fully in Deep Sleep mode. If a wake-up
event occurs before Deep Sleep mode is entered, the
event status will not be reflected in the DSWAKE regis-
ters. If the wake-up source asserts prior to entering
Deep Sleep, the CPU may go to the interrupt vector (if
the wake source has an interrupt bit and the interrupt is
fully enabled), and may abort the Deep Sleep entry
sequence by executing past the SLEEP instruction. In
this case, a wake-up event handler should be placed
after the SLEEP instruction to process the event and
re-attempt entry into Deep Sleep if desired.
When the device is in Deep Sleep with more than one
wake-up source simultaneously enabled, only the first
wake-up source to assert will be detected and logged
in the DSWAKEH/DSWAKEL status registers.
4.6.4
DEEP SLEEP WATCHDOG TIMER
(DSWDT)
(DSWDT)
Deep Sleep has its own dedicated WDT (DSWDT) with
a postscaler for time-outs of 2.1 ms to 25.7 days,
configurable through the bits, DSWDTPS<3:0>
(CONFIG3L<7:4>).
The DSWDT can be clocked from either the INTRC or
the T1OSC/T1CKI input. If the T1OSC/T1CKI source will
be used with a crystal, the T1OSCEN bit in the T1CON
register needs to be set prior to entering Deep Sleep.
The reference clock source is configured through the
DSWDTOSC bit (CONFIG3L<0>).
DSWDT is enabled through the DSWDTEN bit
(CONFIG3L<3>). Entering Deep Sleep mode automati-
cally clears the DSWDT. See
a postscaler for time-outs of 2.1 ms to 25.7 days,
configurable through the bits, DSWDTPS<3:0>
(CONFIG3L<7:4>).
The DSWDT can be clocked from either the INTRC or
the T1OSC/T1CKI input. If the T1OSC/T1CKI source will
be used with a crystal, the T1OSCEN bit in the T1CON
register needs to be set prior to entering Deep Sleep.
The reference clock source is configured through the
DSWDTOSC bit (CONFIG3L<0>).
DSWDT is enabled through the DSWDTEN bit
(CONFIG3L<3>). Entering Deep Sleep mode automati-
cally clears the DSWDT. See
4.6.5
DEEP SLEEP BROWN OUT RESET
(DSBOR)
(DSBOR)
The Deep Sleep module contains a dedicated Deep
Sleep BOR (DSBOR) circuit. This circuit may be
optionally enabled through the DSBOREN Configuration
bit (CONFIG3L<2>).
The DSBOR circuit monitors the V
Sleep BOR (DSBOR) circuit. This circuit may be
optionally enabled through the DSBOREN Configuration
bit (CONFIG3L<2>).
The DSBOR circuit monitors the V
DD
supply rail
voltage. The behavior of the DSBOR circuit is
described in Section 5.4 “Brown-out Reset (BOR)”.
described in Section 5.4 “Brown-out Reset (BOR)”.
4.6.6
RTCC PERIPHERAL AND DEEP
SLEEP
SLEEP
The RTCC can operate uninterrupted during Deep
Sleep mode. It can wake the device from Deep Sleep by
configuring an alarm.
The RTCC clock source is configured with the RTCOSC
bit (CONFIG3L<1>). The available reference clock
sources are the INTRC and T1OSC/T1CKI. If the INTRC
is used, the RTCC accuracy will directly depend on the
INTRC tolerance. For more information on configuring
the RTCC peripheral, see
Sleep mode. It can wake the device from Deep Sleep by
configuring an alarm.
The RTCC clock source is configured with the RTCOSC
bit (CONFIG3L<1>). The available reference clock
sources are the INTRC and T1OSC/T1CKI. If the INTRC
is used, the RTCC accuracy will directly depend on the
INTRC tolerance. For more information on configuring
the RTCC peripheral, see
.