데이터 시트차례Power Management Features with nanoWatt XLP for Extreme Low Power:3Special Microcontroller Features:3Peripheral Highlights:3Peripheral Highlights (Continued):3Flexible Oscillator Structure:3Pin Diagrams5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Table of Contents8Most Current Data Sheet9Errata9Customer Notification System91.0 Device Overview111.1 Core Features111.1.1 nanoWatt Technology111.1.2 Oscillator Options and Features111.1.3 Expanded Memory111.1.4 Extended Instruction Set121.1.5 Easy Migration121.2 Other Special Features121.3 Details on Individual Family Devices12TABLE 1-1: Device Features for the PIC18F2XJ11 (28-pin Devices)13TABLE 1-2: Device Features for the PIC18F4XJ11 (44-pin Devices)13FIGURE 1-1: PIC18F2XJ11 (28-pin) Block Diagram14FIGURE 1-2: PIC18F4XJ11 (44-pin) Block Diagram15TABLE 1-3: PIC18F2XJ11 Pinout I/O Descriptions16TABLE 1-4: PIC18F4XJ11 Pinout I/O Descriptions222.0 Guidelines for Getting Started with PIC18FJ Microcontrollers312.1 Basic Connection Requirements31FIGURE 2-1: Recommended Minimum connections312.2 Power Supply Pins322.2.1 Decoupling Capacitors322.2.2 Tank Capacitors322.3 Master Clear (MCLR) Pin32FIGURE 2-2: Example of MCLR Pin Connections322.4 Voltage Regulator Pins (Vcap/ Vddcore)33FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap33TABLE 2-1: Suitable Capacitor Equivalents332.4.1 Considerations for Ceramic Capacitors34FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics342.5 ICSP Pins342.6 External Oscillator Pins352.7 Unused I/Os35FIGURE 2-5: Suggested Placement of the Oscillator Circuit353.0 Oscillator Configurations373.1 Overview373.1.1 Oscillator Control373.2 Oscillator Types37TABLE 3-1: Oscillator Modes373.2.1 Oscillator Modes38FIGURE 3-1: PIC18F46J11 family Clock Diagram383.2.2 Crystal Oscillator/Ceramic Resonators39FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)39TABLE 3-2: Capacitor Selection for Ceramic Resonators39TABLE 3-3: Capacitor Selection for Crystal Oscillator393.2.3 External Clock Input40FIGURE 3-3: External Clock Input Operation (EC and ECPLL Configuration)403.2.4 PLL Frequency Multiplier403.2.5 Internal Oscillator Block40Register 3-1: OSCTUNE: Oscillator Tuning Register (Access F9Bh)423.3 Clock Sources and Oscillator Switching423.3.1 Oscillator Control Register433.3.2 Oscillator Transitions43Register 3-2: OSCCON: Oscillator Control Register (Access FD3h)443.4 Reference Clock Output45Register 3-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (Banked F3Dh)453.5 Effects of Power-Managed Modes on Various Clock Sources463.6 Power-up Delays464.0 Low-Power Modes474.1 Selecting Power-Managed Modes474.1.1 Clock Sources474.1.2 Entering Power-Managed Modes47TABLE 4-1: Low-Power Modes484.1.3 Clock Transitions and Status Indicators484.1.4 Multiple Sleep Commands484.2 Run Modes484.2.1 PRI_RUN Mode484.2.2 SEC_RUN Mode48FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode49FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)494.2.3 RC_RUN Mode50FIGURE 4-3: Transition Timing to RC_RUN Mode50FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode504.3 Sleep Mode51FIGURE 4-5: Transition Timing for Entry to Sleep Mode51FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)514.4 Idle Modes524.4.1 PRI_IDLE Mode524.4.2 SEC_IDLE Mode52FIGURE 4-7: Transition Timing for Entry to Idle Mode53FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode534.4.3 RC_IDLE Mode544.5 Exiting Idle and Sleep Modes544.5.1 Exit By Interrupt544.5.2 Exit By WDT Time-out544.5.3 Exit By Reset544.5.4 Exit Without an Oscillator Start-up Delay544.6 Deep Sleep Mode544.6.1 Preparing For Deep Sleep554.6.2 I/O PINS DURING DEEP SLEEP554.6.3 Deep Sleep Wake-up Sources564.6.4 Deep Sleep Watchdog Timer (DSWDT)564.6.5 Deep Sleep Brown Out Reset (DSBOR)564.6.6 RTCC Peripheral and Deep Sleep564.6.7 Typical Deep Sleep Sequence574.6.8 Deep Sleep Fault Detection574.6.9 Deep Sleep Mode Registers58Register 4-1: DSCONH: Deep Sleep Control High Byte Register (Banked F4Dh)58Register 4-2: DSCONL: Deep Sleep Control Low Byte Register (Banked F4Ch)58Register 4-3: DSGPR0: Deep Sleep Persistent General Purpose Register 0 (Banked F4Eh)59Register 4-4: DSGPR1: Deep Sleep Persistent General Purpose Register 1 (Banked F4Fh)59Register 4-5: DSWAKEH: Deep Sleep Wake High Byte Register (Banked F4Bh)60Register 4-6: DSWAKEL: Deep Sleep Wake Low Byte Register (Banked F4Ah)604.7 Ultra Low-Power Wake-up61FIGURE 4-9: Serial Resistor61EXAMPLE 4-1: Ultra Low-Power Wake-up Initialization625.0 Reset635.1 RCON Register63FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit63Register 5-1: RCON: Reset Control Register (Access FD0h)645.2 Master Clear (MCLR)655.3 Power-on Reset (POR)655.4 Brown-out Reset (BOR)655.4.1 Detecting BOR655.5 Configuration Mismatch (CM)665.6 Power-up Timer (PWRT)665.6.1 Time-out Sequence66FIGURE 5-2: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)66FIGURE 5-3: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 167FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 267FIGURE 5-5: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)675.7 Reset State of Registers68TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register68TABLE 5-2: Initialization Conditions for All Registers696.0 Memory Organization776.1 Program Memory Organization77FIGURE 6-1: Memory Maps for PIC18F46J11 family Devices776.1.1 Hard Memory Vectors78FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F46J11 family Devices786.1.2 Flash Configuration Words78TABLE 6-1: Flash Configuration Word for PIC18F46J11 family Devices786.1.3 Program Counter796.1.4 Return Address Stack79FIGURE 6-3: Return Address Stack and Associated Registers79Register 6-1: STKPTR: Stack Pointer Register (Access FFCh)806.1.5 Fast Register Stack (FRS)81EXAMPLE 6-1: Fast Register Stack Code Example816.1.6 Look-up Tables in Program Memory81EXAMPLE 6-2: Computed GOTO Using an Offset Value816.2 PIC18 Instruction Cycle826.2.1 Clocking Scheme826.2.2 Instruction Flow/Pipelining82FIGURE 6-4: Clock/ Instruction Cycle82EXAMPLE 6-3: Instruction Pipeline Flow826.2.3 Instructions in Program Memory83FIGURE 6-5: Instructions in Program Memory836.2.4 Two-Word Instructions83EXAMPLE 6-4: Two-Word Instructions836.3 Data Memory Organization846.3.1 Bank Select Register84FIGURE 6-6: Data Memory Map for PIC18F46J11 family Devices85FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)866.3.2 Access Bank866.3.3 General Purpose Register File866.3.4 Special Function Registers87TABLE 6-2: Access Bank Special Function Register Map87TABLE 6-3: Non-Access Bank Special Function Register Map88TABLE 6-4: Register File Summary (PIC18F46J11 Family)906.3.5 STATUS Register96Register 6-2: Status Register (Access FD8h)966.4 Data Addressing Modes976.4.1 Inherent and Literal Addressing976.4.2 Direct Addressing976.4.3 Indirect Addressing97EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing97FIGURE 6-8: Indirect Addressing986.5 Program Memory and the Extended Instruction Set996.6 Data Memory and the Extended Instruction Set996.6.1 Indexed Addressing with Literal Offset1006.6.2 Instructions Affected By Indexed Literal Offset Mode100FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)1016.6.3 Mapping the Access Bank in Indexed Literal Offset Mode1026.6.4 BSR in Indexed Literal Offset Mode102FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing1027.0 Flash Program Memory1037.1 Table Reads and Table Writes103FIGURE 7-1: TABLE READ Operation103FIGURE 7-2: TABLE WRITE Operation1047.2 Control Registers1047.2.1 EECON1 and EECON2 Registers104Register 7-1: EECON1: EEPROM Control Register 1 (Access FA6h)1057.2.2 Table Latch Register (TABLAT)1067.2.3 Table Pointer Register (TBLPTR)1067.2.4 Table Pointer Boundaries106TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions106FIGURE 7-3: Table Pointer Boundaries Based on Operation1067.3 Reading the Flash Program Memory107FIGURE 7-4: Reads from Flash Program Memory107EXAMPLE 7-1: Reading a Flash Program Memory Word1077.4 Erasing Flash Program Memory1087.4.1 Flash Program Memory Erase Sequence108EXAMPLE 7-2: Erasing Flash Program Memory1087.5 Writing to Flash Program Memory109FIGURE 7-5: Table Writes to Flash Program Memory1097.5.1 Flash Program Memory Write Sequence109EXAMPLE 7-3: Writing to Flash Program Memory1107.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING).111EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY1117.5.3 Write Verify1127.5.4 Unexpected Termination of Write Operation1127.6 Flash Program Operation During Code Protection112TABLE 7-2: Registers Associated with Program Flash Memory1128.0 8 X 8 Hardware Multiplier1138.1 Introduction1138.2 Operation113EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine113EXAMPLE 8-2: 8 x 8 Signed Multiply Routine113TABLE 8-1: Performance Comparison for Various Multiply Operations113EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm114EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine114EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm114EXAMPLE 8-4: 16 x 16 Signed Multiply Routine1149.0 Interrupts115FIGURE 9-1: PIC18F46J11 family Interrupt Logic1169.1 INTCON Registers117Register 9-1: INTCON: Interrupt Control Register (Access FF2h)117Register 9-2: INTCON2: Interrupt Control Register 2 (Access FF1h)118Register 9-3: INTCON3: Interrupt Control Register 3 (Access FF0h)1199.2 PIR Registers120Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1 (Access F9Eh)120Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2 (Access FA1h)121Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3 (Access FA4h)1229.3 PIE Registers123Register 9-7: PIE1: Peripheral Interrupt Enable Register 1 (Access F9Dh)123Register 9-8: PIE2: Peripheral Interrupt Enable Register 2 (Access FA0h)124Register 9-9: PIE3: Peripheral Interrupt Enable Register 3 (Access FA3h)1259.4 IPR Registers126Register 9-10: IPR1: Peripheral Interrupt Priority Register 1 (Access F9Fh)126Register 9-11: IPR2: Peripheral Interrupt Priority Register 2 (Access FA2h)127Register 9-12: IPR3: Peripheral Interrupt Priority Register 3 (Access FA5h)1289.5 RCON Register129Register 9-13: RCON: Reset Control Register (Access FD0h)1299.6 INTx Pin Interrupts1309.7 TMR0 Interrupt1309.8 PORTB Interrupt-on-Change1309.9 Context Saving During Interrupts130EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM13010.0 I/O Ports131FIGURE 10-1: Generic I/O Port Operation13110.1 I/O Port Pin Capabilities13110.1.1 Pin Output Drive131TABLE 10-1: Output Drive Levels13110.1.2 Input Pins and Voltage Considerations131TABLE 10-2: Input Voltage Levels13110.1.3 Interfacing to a 5V System132FIGURE 10-2: +5V System Hardware Interface132EXAMPLE 10-1: Communicating with the +5V System13210.1.4 Open-Drain Outputs132FIGURE 10-3: Using the Open-Drain Output (USART Shown as Example)13210.1.5 TTL Input Buffer Option132Register 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL Register 1 (Banked F42h)133Register 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL Register 2 (Banked F41h)133Register 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL Register 3 (Banked F40h)134Register 10-4: PADCFG1: Pad Configuration Control Register 1 (Banked F3Ch)13410.2 PORTA, TRISA and LATA Registers135EXAMPLE 10-2: Initializing PORTA135TABLE 10-3: PORTA I/O Summary136TABLE 10-4: Summary of Registers Associated with PORTA13710.3 PORTB, TRISB and LATB Registers138EXAMPLE 10-3: Initializing PORTB138TABLE 10-5: PORTB I/O Summary139TABLE 10-6: Summary of Registers Associated with PORTB14110.4 PORTC, TRISC and LATC Registers142EXAMPLE 10-4: Initializing PORTC142TABLE 10-7: PORTC I/O Summary143TABLE 10-8: Summary of Registers Associated with PORTC14410.5 PORTD, TRISD and LATD Registers145EXAMPLE 10-5: Initializing PORTD145TABLE 10-9: PORTD I/O Summary146TABLE 10-10: Summary of Registers Associated with PORTD14710.6 PORTE, TRISE and LATE Registers148EXAMPLE 10-6: Initializing PORTE148TABLE 10-11: PORTE I/O Summary149TABLE 10-12: Summary of Registers Associated with PORTE14910.7 Peripheral Pin Select (PPS)15010.7.1 Available Pins15010.7.2 Available Peripherals15010.7.3 Controlling Peripheral Pin Select150TABLE 10-13: Selectable INPUT SOURCES (MAPS Input TO FUNCTION)(1)151TABLE 10-14: Selectable OUTPUT SOURCES (MAPS Function TO Output)15210.7.4 Controlling Configuration Changes15310.7.5 Considerations for Peripheral Pin Selection153EXAMPLE 10-7: Configuring EUSART2 Input and OUtput Functions15410.7.6 Peripheral Pin Select Registers155Register 10-5: PPSCON: Peripheral Pin Select Input Register 0 (Banked EFFh)(1)155Register 10-6: RPINR1: Peripheral Pin Select Input Register 1 (Banked EE7h)156Register 10-7: RPINR2: Peripheral Pin Select Input Register 2 (Banked EE8h)156Register 10-8: RPINR3: Peripheral Pin Select Input Register 3 (Banked EE9h)156Register 10-9: RPINR4: Peripheral Pin Select Input Register 4 (Banked EEAh)157Register 10-10: RPINR6: Peripheral Pin Select Input Register 6 (Banked EECh)157Register 10-11: RPINR7: Peripheral Pin Select Input Register 7 (Banked EEDh)157Register 10-12: RPINR8: Peripheral Pin Select Input Register 8 (Banked EEEh)158Register 10-13: RPINR12: Peripheral Pin Select Input Register 12 (Banked EF2h)158Register 10-14: RPINR13: Peripheral Pin Select Input Register 13 (Banked EF3h)158Register 10-15: RPINR16: Peripheral Pin Select Input Register 16 (Banked EF6h)159Register 10-16: RPINR17: Peripheral Pin Select Input Register 17 (Banked EF7h)159Register 10-17: RPINR21: Peripheral Pin Select Input Register 21 (Banked EFBh)159Register 10-18: RPINR22: Peripheral Pin Select Input Register 22 (Banked EFCh)160Register 10-19: RPINR23: Peripheral Pin Select Input Register 23 (Banked EFDh)160Register 10-20: RPINR24: Peripheral Pin Select Input Register 24 (Banked EFEh)160Register 10-21: RPOR0: Peripheral Pin Select Output Register 0 (Banked EC6h)(1)161Register 10-22: RPOR1: Peripheral Pin Select Output Register 1 (Banked EC7h)161Register 10-23: RPOR2: Peripheral Pin Select Output Register 2 (Banked EC8h)161Register 10-24: RPOR3: Peripheral Pin Select Output Register 3 (Banked EC9h)162Register 10-25: RPOR4: Peripheral Pin Select Output Register 4 (Banked ECAh)162Register 10-26: RPOR5: Peripheral Pin Select Output Register 5 (Banked ECBh)162Register 10-27: RPOR6: Peripheral Pin Select Output Register 6 (Banked ECCh)163Register 10-28: RPOR7: Peripheral Pin Select Output Register 7 (Banked ECDh)163Register 10-29: RPOR8: Peripheral Pin Select Output Register 8 (Banked ECEh)163Register 10-30: RPOR9: Peripheral Pin Select Output Register 9 (Banked ECFh)164Register 10-31: RPOR10: Peripheral Pin Select Output Register 10 (Banked ED0h)164Register 10-32: RPOR11: Peripheral Pin Select Output Register 11 (Banked ED1h)164Register 10-33: RPOR12: Peripheral Pin Select Output Register 12 (Banked ED2h)165Register 10-34: RPOR13: Peripheral Pin Select Output Register 13 (Banked ED3h)165Register 10-35: RPOR14: Peripheral Pin Select Output Register 14 (Banked ED4h)165Register 10-36: RPOR15: Peripheral Pin Select Output Register 15 (Banked ED5h)166Register 10-37: RPOR16: Peripheral Pin Select Output Register 16 (Banked ED6h)166Register 10-38: RPOR17: Peripheral Pin Select Output Register 17 (Banked ED7h)166Register 10-39: RPOR18: Peripheral Pin Select Output Register 18 (Banked ED8h)167Register 10-40: RPOR19: Peripheral Pin Select Output Register 19 (Banked ED9h)(1)167Register 10-41: RPOR20: Peripheral Pin Select Output Register 20 (Banked EDAh)(1)167Register 10-42: RPOR21: Peripheral Pin Select Output Register 21 (Banked EDBh)(1)168Register 10-43: RPOR22: Peripheral Pin Select Output Register 22 (Banked EDCh)(1)168Register 10-44: RPOR23: Peripheral Pin Select Output Register 23 (Banked EDDh)(1)168Register 10-45: RPOR24: Peripheral Pin Select Output Register 24 (Banked EDEh)(1)16911.0 Parallel Master Port (PMP)171FIGURE 11-1: PMP Module Overview17111.1 Module Registers17211.1.1 CONTROL REGISTERS172Register 11-1: PMCONH: Parallel Port Control Register High Byte (Banked F5Fh)(1)172Register 11-2: PMCONL: Parallel Port Control Register Low Byte (Banked F5Eh)(1)173Register 11-3: PMMODEH: Parallel Port Mode Register High Byte (Banked F5Dh)(1)174Register 11-4: PMMODEL: Parallel Port Mode Register Low Byte (Banked F5Ch)(1)175Register 11-5: PMEH: Parallel Port Enable Register High Byte (Banked F57h)(1)176Register 11-6: PMEL: Parallel Port Enable Register Low Byte (Banked F56h)(1)176Register 11-7: PMSTATH: Parallel Port Status Register High Byte (Banked F55h)(1)177Register 11-8: PMSTATL: Parallel Port Status Register Low Byte (Banked F54h)(1)17711.1.2 Data Registers17811.1.3 Pad Configuration Control Register178Register 11-9: PMADDRH: Parallel Port Address Register HIGH BYTE – MASTER MODES ONLY (Access F6Fh)(1)179Register 11-10: PMADDRL: Parallel Port Address Register Low BYTE – MASTER MODES ONLY (Access F6Eh)(1)17911.2 Slave Port Modes18011.2.1 Legacy Mode (PSP)180FIGURE 11-2: Legacy Parallel Slave Port Example18011.2.2 WRITE TO SLAVE PORT18111.2.3 READ FROM SLAVE PORT181FIGURE 11-3: Parallel Slave Port Write Waveforms181FIGURE 11-4: Parallel Slave Port Read Waveforms18111.2.4 Buffered Parallel Slave Port Mode182FIGURE 11-5: Parallel Master/Slave Connection Buffered Example18211.2.5 Addressable Parallel Slave Port Mode183TABLE 11-1: Slave Mode Buffer Addressing183FIGURE 11-6: Parallel Master/Slave Connection Addressed Buffer Example183FIGURE 11-7: Parallel Slave Port Read Waveforms183FIGURE 11-8: Parallel Slave Port Write Waveforms18411.3 MASTER PORT MODES18511.3.1 PMP and I/O Pin Control18511.3.2 READ/WRITE CONTROL18511.3.3 DATA WIDTH18511.3.4 ADDRESS MULTIPLEXING185FIGURE 11-9: Demultiplexed Addressing Mode (Separate Read and Write Strobes with Chip Select)186FIGURE 11-10: Partially Multiplexed Addressing Mode (Separate Read and Write Strobes with Chip Select)186FIGURE 11-11: Fully Multiplexed Addressing Mode (Separate Read and Write Strobes with Chip Select)18611.3.5 Chip Select Features18711.3.6 AUTO-INCREMENT/DECREMENT18711.3.7 WAIT STATES18711.3.8 Read Operation18711.3.9 Write Operation18711.3.10 Parallel Master Port Status18711.3.11 Master Mode Timing188FIGURE 11-12: Read and Write Timing, 8-bit Data, Demultiplexed Address188FIGURE 11-13: Read Timing, 8-bit Data, Partially Multiplexed Address188FIGURE 11-14: Read Timing, 8-bit Data, Wait States Enabled, Partially Multiplexed Address188FIGURE 11-15: Write Timing, 8-bit Data, Partially Multiplexed Address189FIGURE 11-16: Write Timing, 8-bit Data, Wait States Enabled, Partially Multiplexed Address189FIGURE 11-17: Read Timing, 8-bit Data, Partially Multiplexed Address, Enable Strobe189FIGURE 11-18: Write Timing, 8-bit Data, Partially Multiplexed Address, Enable Strobe190FIGURE 11-19: Read Timing, 8-bit Data, Fully Multiplexed 16-bit Address190FIGURE 11-20: Write Timing, 8-bit Data, Fully Multiplexed 16-bit Address190FIGURE 11-21: Read Timing, 16-bit Data, Demultiplexed Address191FIGURE 11-22: Write Timing, 16-bit Data, Demultiplexed Address191FIGURE 11-23: Read Timing, 16-bit Multiplexed Data, Partially Multiplexed Address191FIGURE 11-24: Write Timing, 16-bit Multiplexed Data, Partially Multiplexed Address192FIGURE 11-25: Read Timing, 16-bit Multiplexed Data, Fully Multiplexed 16-bit Address192FIGURE 11-26: Write Timing, 16-bit Multiplexed Data, Fully Multiplexed 16-bit Address19211.4 Application Examples19311.4.1 Multiplexed Memory or Peripheral193FIGURE 11-27: Example – Multiplexed Addressing Application19311.4.2 Partially Multiplexed Memory or Peripheral193FIGURE 11-28: Example of a Partially Multiplexed Addressing Application193FIGURE 11-29: Example of an 8-bit Multiplexed Address and Data Application19311.4.3 Parallel EEPROM Example194FIGURE 11-30: Parallel EEPROM Example (Up to 15-bit Address, 8-bit Data)194FIGURE 11-31: Parallel EEPROM Example (Up to 15-bit Address, 16-bit Data)19411.4.4 LCD Controller Example194FIGURE 11-32: LCD Control Example (Byte Mode Operation)194TABLE 11-2: Registers Associated with PMP Module19512.0 Timer0 Module197Register 12-1: T0CON: Timer0 Control Register (Access FD5h)19712.1 Timer0 Operation19812.2 Timer0 Reads and Writes in 16-Bit Mode198FIGURE 12-1: Timer0 Block Diagram (8-bit Mode)198FIGURE 12-2: Timer0 Block Diagram (16-bit Mode)19812.3 Prescaler19912.3.1 Switching Prescaler Assignment19912.4 Timer0 Interrupt199TABLE 12-1: Registers Associated with Timer019913.0 Timer1 Module201Register 13-1: T1CON: Timer1 Control Register (Access FCDh)20113.1 Timer1 Gate Control Register202Register 13-2: T1GCON: Timer1 Gate Control Register (F9Ah)(1)202Register 13-3: TCLKCON: Timer clock control register (Banked F52h)20313.2 Timer1 Operation20413.3 Clock Source Selection20413.3.1 INTERNAL CLOCK SOURCE20413.3.2 EXTERNAL CLOCK SOURCE204TABLE 13-1: Timer1 Clock Source Selection204FIGURE 13-1: Timer1 Block Diagram20513.4 Timer1 16-Bit Read/Write Mode20613.5 Timer1 Oscillator206FIGURE 13-2: External Components for the Timer1 LP Oscillator206TABLE 13-2: Capacitor Selection for the Timer Oscillator(2,3,4,5)20613.5.1 Using Timer1 as a Clock Source20713.5.2 Timer1 Oscillator Layout Considerations207FIGURE 13-3: Oscillator Circuit with Grounded Guard Ring20713.6 Timer1 Interrupt20713.7 Resetting Timer1 Using the ECCP Special Event Trigger20813.8 Timer1 Gate20813.8.1 TIMER1 GATE COUNT ENABLE208TABLE 13-3: TIMER1 GATE ENABLE SELECTIONS208FIGURE 13-4: Timer1 Gate Count Enable Mode20913.8.2 TIMER1 GATE SOURCE SELECTION209TABLE 13-4: TIMER1 GATE SOURCES20913.8.3 TIMER1 GATE TOGGLE MODE210FIGURE 13-5: Timer1 Gate Toggle Mode21013.8.4 TIMER1 GATE SINGLE PULSE MODE21113.8.5 TIMER1 GATE VALUE STATUS211FIGURE 13-6: Timer1 Gate Single Pulse Mode211FIGURE 13-7: Timer1 Gate Single Pulse and Toggle Combined Mode212TABLE 13-5: Registers Associated with Timer1 as a Timer/Counter21214.0 Timer2 Module21314.1 Timer2 Operation213Register 14-1: T2CON: Timer2 Control Register (Access FCAh)21314.2 Timer2 Interrupt21414.3 Timer2 Output214FIGURE 14-1: Timer2 Block Diagram214TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter21415.0 Timer3 Module215Register 15-1: T3CON: Timer3 Control Register (Access F79h)21515.1 Timer3 Gate Control Register216Register 15-2: T3GCON: Timer3 Gate Control Register (Access F97h)(1)216Register 15-3: TCLKCON: Timer clock control register (Banked F52h)21715.2 Timer3 Operation218FIGURE 15-1: Timer3 Block Diagram21815.3 Timer3 16-Bit Read/Write Mode21915.4 Using the Timer1 Oscillator as the Timer3 Clock Source21915.5 Timer3 Gate21915.5.1 TIMER3 GATE COUNT ENABLE219TABLE 15-1: TIMER3 GATE ENABLE SELECTIONS219FIGURE 15-2: Timer3 Gate Count Enable Mode21915.5.2 TIMER3 GATE SOURCE SELECTION220TABLE 15-2: TIMER3 GATE SOURCES22015.5.3 TIMER3 GATE TOGGLE MODE220FIGURE 15-3: Timer3 Gate Toggle Mode22015.5.4 TIMER3 GATE SINGLE PULSE MODE221FIGURE 15-4: Timer3 Gate Single Pulse Mode221FIGURE 15-5: Timer3 Gate Single Pulse and Toggle Combined Mode22215.5.5 TIMER3 GATE VALUE STATUS22215.5.6 TIMER3 GATE EVENT INTERRUPT22215.6 Timer3 Interrupt22315.7 Resetting Timer3 Using the ECCP Special Event Trigger223TABLE 15-3: Registers Associated with Timer3 as a Timer/Counter22316.0 Timer4 Module22516.1 Timer4 Operation225Register 16-1: T4CON: Timer4 Control Register (Access F76h)22516.2 Timer4 Interrupt22616.3 Output of TMR4226FIGURE 16-1: Timer4 Block Diagram226TABLE 16-1: Registers Associated with Timer4 as a Timer/Counter22617.0 Real-Time Clock and Calendar (RTCC)227FIGURE 17-1: RTCC Block Diagram22717.1 RTCC Module Registers228RTCC Control Registers228RTCC Value Registers228Alarm Value Registers22817.1.1 RTCC Control Registers229Register 17-1: RTCCFG: RTCC Configuration Register (Banked F3Fh)(1)229Register 17-2: RTCCAL: RTCC Calibration Register (Banked F3Eh)230Register 17-3: PADCFG1: Pad Configuration Register (Banked F3Ch)230Register 17-4: ALRMCFG: Alarm Configuration Register (Access F91h)231Register 17-5: ALRMRPT: Alarm Repeat Counter (Access F90h)23217.1.2 RTCVALH and RTCVALL Register Mappings233Register 17-6: Reserved Register (Access F99h, PTR 11b)233Register 17-7: Year: Year Value Register (Access F98h, PTR 11b)(1)233Register 17-8: MONTH: Month Value Register (Access F99h, PTR 10b)(1)233Register 17-9: DAY: Day Value Register (Access F98h, PTR 10b)(1)234Register 17-10: WKDY: Weekday Value Register (Access F99h, PTR 01b)(1)234Register 17-11: HOURS: Hours Value Register (Access F98h, PTR 01b)(1)235Register 17-12: MINUTES: Minutes Value Register (Access F99h, PTR 00b)235Register 17-13: SECONDS: Seconds Value Register (Access F98h, PTR 00b)23517.1.3 ALRMVALH and ALRMVALL Register Mappings236Register 17-14: ALRMMNTH: Alarm Month Value Register (Access F8Fh, PTR 10b)(1)236Register 17-15: ALRMDAY: Alarm Day Value Register (Access F8Eh, PTR 10b)(1)236Register 17-16: ALRMWd: Alarm Weekday Value Register (Access F8Fh, PTR 01b)(1)237Register 17-17: ALRMHr: Alarm Hours Value Register (Access F8Eh, PTR 01b)(1)237Register 17-18: ALRMMIN: Alarm Minutes Value Register (Access F8Fh, PTR 00b)238Register 17-19: ALRMSEC: Alarm Seconds Value Register (Access F8Eh, PTR 00b)23817.1.4 RTCEN Bit Write23917.2 Operation23917.2.1 Register Interface239FIGURE 17-2: Timer Digit Format239FIGURE 17-3: Alarm Digit Format23917.2.2 Clock Source240FIGURE 17-4: Clock Source Multiplexing24017.2.3 Digit Carry Rules240TABLE 17-1: Day of Week Schedule240TABLE 17-2: Day to Month Rollover Schedule24117.2.4 Leap Year24117.2.5 General Functionality24117.2.6 Safety Window for Register Reads and Writes24117.2.7 Write Lock241EXAMPLE 17-1: Setting the RTCWREN Bit24117.2.8 Register Mapping241TABLE 17-3: RTCVALH and RTCVALL Register Mapping242TABLE 17-4: ALRMVAL Register Mapping24217.2.9 Calibration242EQUATION 17-1: Converting Error Clock Pulses24217.3 Alarm24317.3.1 Configuring the Alarm243FIGURE 17-5: Alarm Mask Settings24317.3.2 Alarm Interrupt244FIGURE 17-6: Timer Pulse Generation24417.4 Low-Power Modes24417.5 Reset24417.5.1 Device Reset24417.5.2 Power-on Reset (POR)24417.6 Register Maps245TABLE 17-5: RTCC Control Registers245TABLE 17-6: RTCC Value Registers245TABLE 17-7: Alarm Value Registers24518.0 Enhanced Capture/Compare/PWM (ECCP) Module247Register 18-1: CCPxCON: ECCPx Control (Access FBAh/FB4h)24818.1 ECCP Outputs and Configuration24918.1.1 ECCP Module and Timer Resources249TABLE 18-1: ECCP Mode – Timer Resource24918.2 Capture Mode24918.2.1 ECCP Pin Configuration24918.2.2 Timer1/Timer3 Mode Selection24918.2.3 Software Interrupt24918.2.4 ECCP Prescaler250EXAMPLE 18-1: Changing Between Capture Prescalers250FIGURE 18-1: Capture Mode Operation Block Diagram25018.3 Compare Mode25118.3.1 ECCP Pin Configuration25118.3.2 Timer1/Timer3 Mode Selection25118.3.3 Software Interrupt Mode25118.3.4 Special Event Trigger251FIGURE 18-2: Compare Mode Operation Block Diagram25118.4 PWM Mode252FIGURE 18-3: Simplified PWM Block Diagram252FIGURE 18-4: PWM Output25218.4.1 PWM Period252EQUATION 18-1:25218.4.2 PWM Duty Cycle252EQUATION 18-2:252EQUATION 18-3:25318.4.3 Setup for PWM Operation253TABLE 18-2: Example PWM Frequencies and Resolutions at 40 MHz253TABLE 18-3: Registers Associated with PWM, Timer2 and Timer425418.5 PWM (Enhanced Mode)255FIGURE 18-5: Example Simplified Block Diagram of the Enhanced PWM Mode255TABLE 18-4: Example Pin Assignments for Various PWM Enhanced Modes256FIGURE 18-6: Example PWM (enhanced Mode) Output Relationships (Active-High State)256FIGURE 18-7: Example Enhanced PWM Output Relationships (Active-Low State)25718.5.1 Half-Bridge Mode258FIGURE 18-8: Example of Half-Bridge PWM Output258FIGURE 18-9: Example of Half-Bridge Applications25818.5.2 Full-Bridge Mode259FIGURE 18-10: Example of Full-Bridge Application259FIGURE 18-11: Example of Full-Bridge PWM Output260FIGURE 18-12: Example of PWM Direction Change261FIGURE 18-13: Example of PWM Direction Change at Near 100% Duty Cycle26218.5.3 Start-up Considerations26218.5.4 Enhanced PWM Auto-shutdown mode263Register 18-2: ECCPxAS: ECCPx Auto-Shutdown Control Register (Access FBEh/FB8h)263FIGURE 18-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)26418.5.5 Auto-Restart Mode264FIGURE 18-15: PWM Auto-shutdown With Auto-Restart Enabled (PxRSEN = 1)26418.5.6 Programmable Dead-Band Delay Mode265FIGURE 18-16: Example of Half-Bridge PWM Output265FIGURE 18-17: Example of Half-Bridge Applications265Register 18-3: ECCPxDEL: Enhanced PWM Control Register (Access FBDh/FB7h)26618.5.7 Pulse Steering Mode266Register 18-4: PSTRxCON: Pulse Steering Control (Access FBFh/FB9h)(1)267FIGURE 18-18: Simplified Steering Block Diagram268FIGURE 18-19: Example of Steering Event at End of Instruction (STRSYNC = 0)268FIGURE 18-20: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)26818.5.8 Operation in Power-Managed Modes26918.5.9 Effects of a Reset269TABLE 18-5: Registers Associated with ECCP1 Module and Timer1 to Timer326919.0 Master Synchronous Serial Port (MSSP) Module27119.1 Master SSP (MSSP) Module Overview27119.2 Control Registers27219.3 SPI Mode272FIGURE 19-1: MSSPx Block Diagram (SPI Mode)27219.3.1 Registers273Register 19-1: SSPxSTAT: MSSPx Status Register – SPI Mode (Access FC7h/F73h)273Register 19-2: SSPxCON1: MSSPx Control Register 1 – SPI Mode (Access FC6h/F72h)27419.3.2 Operation27519.3.3 Open-Drain Output Option275EXAMPLE 19-1: Loading the SSP1BUF (SSP1SR) Register27519.3.4 Enabling SPI I/O27619.3.5 Typical Connection276FIGURE 19-2: SPI Master/Slave Connection27619.3.6 Master Mode277FIGURE 19-3: SPI Mode Waveform (Master Mode)27719.3.7 Slave Mode27819.3.8 Slave Select Synchronization278FIGURE 19-4: Slave Synchronization Waveform278FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0)279FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1)27919.3.9 Operation in Power-Managed Modes28019.3.10 Effects of a Reset28019.3.11 Bus Mode Compatibility280TABLE 19-1: SPI Bus Modes28019.3.12 SPI Clock Speed and Module Interactions280TABLE 19-2: Registers Associated with SPI Operation28119.4 SPI DMA Module28219.4.1 I/O PIN CONSIDERATIONS28219.4.2 RAM TO RAM COPY OPERATIONS28219.4.3 IDLE AND SLEEP CONSIDERATIONS28219.4.4 REGISTERS282Register 19-3: DMACON1: DMA Control Register 1 (Access F88h)284Register 19-4: DMACON2: DMA Control Register 2 (Access F86h)285EQUATION 19-1: BYTES TRANSMITTED FOR A GIVEN DMABC28719.4.5 INTERRUPTS28719.4.6 Using the SPI DMA Module288EXAMPLE 19-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER28919.5 I2C Mode291FIGURE 19-7: MSSPx Block Diagram (I2C™ Mode)29119.5.1 Registers291Register 19-5: SSPxSTAT: MSSPx Status Register – I2C™ Mode (Access FC7h/F73h)292Register 19-6: SSPxCON1: MSSPx Control Register 1 – I2C™ Mode (Access FC6h/F72h)293Register 19-7: SSPxCON2: MSSPx Control Register 2 –I2C™ Master Mode (Access FC5h/F71h)294Register 19-8: SSPxCON2: MSSPx Control Register 2 – I2C™ Slave Mode (Access FC5h/F71h)295Register 19-9: SSPxMSK: I2C™ Slave Address Mask Register – 7-bit Masking Mode (Access FC8h/F74h)(1)29519.5.2 Operation29619.5.3 Slave Mode296EXAMPLE 19-3: Address Masking Examples in 5-bit Masking Mode297EXAMPLE 19-4: Address Masking Examples in 7-Bit Masking Mode298FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)300FIGURE 19-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)301FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)302FIGURE 19-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)303FIGURE 19-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)304FIGURE 19-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)30519.5.4 Clock Stretching306FIGURE 19-14: Clock Synchronization Timing307FIGURE 19-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)308FIGURE 19-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)30919.5.5 General Call Address Support310FIGURE 19-17: Slave Mode General Call Address Sequence (7-Bit or 10-bit Addressing Mode)31019.5.6 Master Mode310FIGURE 19-18: MSSPx Block Diagram (I2C™ Master Mode)31119.5.7 Baud Rate312FIGURE 19-19: Baud Rate Generator Block Diagram313TABLE 19-3: I2C™ Clock Rate w/BRG313FIGURE 19-20: Baud Rate Generator Timing with Clock Arbitration31419.5.8 I2C Master Mode Start Condition Timing314FIGURE 19-21: First Start Bit Timing31419.5.9 I2C Master Mode Repeated Start Condition Timing315FIGURE 19-22: Repeated Start Condition Waveform31519.5.10 I2C Master Mode Transmission31619.5.11 I2C Master Mode Reception316FIGURE 19-23: I2C™ Master Mode Waveform (Transmission, 7-Bit or 10-bit Address)317FIGURE 19-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)31819.5.12 Acknowledge Sequence Timing31919.5.13 Stop Condition Timing319FIGURE 19-25: Acknowledge Sequence Waveform319FIGURE 19-26: Stop Condition Receive or Transmit Mode31919.5.14 Sleep Operation32019.5.15 Effects of a Reset32019.5.16 Multi-master Mode32019.5.17 Multi -master Communication, Bus Collision and Bus Arbitration320FIGURE 19-27: Bus Collision Timing for Transmit and Acknowledge320FIGURE 19-28: Bus Collision During Start Condition (SDAx Only)321FIGURE 19-29: Bus Collision During Start Condition (SCLx = 0)322FIGURE 19-30: BRG Reset Due to SDAx Arbitration During Start Condition322FIGURE 19-31: Bus Collision During a Repeated Start Condition (Case 1)323FIGURE 19-32: Bus Collision During Repeated Start Condition (Case 2)323FIGURE 19-33: Bus Collision During a Stop Condition (Case 1)324FIGURE 19-34: Bus Collision During a Stop Condition (Case 2)324TABLE 19-4: Registers Associated with I2C™ Operation32520.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)327Register 20-1: TXSTAx: Transmit Status And Control Register (Access FADh/FA8h)328Register 20-2: RCSTAx: Receive Status And Control Register (Access FACh/F9Ch)329Register 20-3: BAUDCONx: Baud Rate Control Register (Access F7Eh/F7Ch)33020.1 Baud Rate Generator (BRG)33120.1.1 Operation in Power-Managed Modes33120.1.2 Sampling331TABLE 20-1: Baud Rate Formulas331EXAMPLE 20-1: Calculating Baud Rate Error332TABLE 20-2: Registers Associated with Baud Rate Generator332TABLE 20-3: Baud Rates for Asynchronous Modes33320.1.3 Auto-Baud Rate Detect335TABLE 20-4: BRG Counter Clock Rates335FIGURE 20-1: Automatic Baud Rate Calculation336FIGURE 20-2: BRG Overflow Sequence33620.2 EUSART Asynchronous Mode33720.2.1 EUSART Asynchronous Transmitter337FIGURE 20-3: EUSART Transmit Block Diagram337FIGURE 20-4: Asynchronous Transmission338FIGURE 20-5: Asynchronous Transmission (Back-to-Back)338TABLE 20-5: Registers Associated with Asynchronous Transmission33820.2.2 EUSART Asynchronous Receiver33920.2.3 Setting Up 9-bit Mode with Address Detect339FIGURE 20-6: EUSARTx Receive Block Diagram340FIGURE 20-7: Asynchronous Reception340TABLE 20-6: Registers Associated with Asynchronous Reception34120.2.4 Auto-Wake-up on Sync Break Character341FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation342FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep34220.2.5 Break Character Sequence34320.2.6 Receiving A Break Character343FIGURE 20-10: Send Break Character Sequence34320.3 EUSART Synchronous Master Mode34420.3.1 EUSART Synchronous Master Transmission344FIGURE 20-11: Synchronous Transmission344FIGURE 20-12: Synchronous Transmission (Through TXEN)345TABLE 20-7: Registers Associated with Synchronous Master Transmission34520.3.2 EUSART Synchronous Master Reception346FIGURE 20-13: Synchronous Reception (Master Mode, SREN)346TABLE 20-8: Registers Associated with Synchronous Master Reception34720.4 EUSART Synchronous Slave Mode34820.4.1 EUSART Synchronous Slave Transmission348TABLE 20-9: Registers Associated with Synchronous Slave Transmission34920.4.2 EUSART Synchronous Slave Reception350TABLE 20-10: Registers Associated with Synchronous Slave Reception35021.0 10-bit Analog-to-Digital Converter (A/D) Module351Register 21-1: ADCON0: A/D Control Register 0 (Access FC2h)351Register 21-2: ADCON1: A/D Control Register 1 (Access FC1h)352Register 21-3: ANCON0: A/D Port Configuration Register 2 (Banked F48h)353Register 21-4: ANCON1: A/D Port Configuration Register 1 (Banked F49h)353FIGURE 21-1: A/D Block Diagram354FIGURE 21-2: Analog Input Model35521.1 A/D Acquisition Requirements356EQUATION 21-1: Acquisition Time356EQUATION 21-2: A/D Minimum Charging Time356EQUATION 21-3: Calculating the Minimum Required Acquisition Time35621.2 Selecting and Configuring Automatic Acquisition Time35721.3 Selecting the A/D Conversion Clock357TABLE 21-1: Tad vs. Device Operating Frequencies35721.4 Configuring Analog Port Pins35721.5 A/D Conversions35821.6 Use of the ECCP2 Trigger358FIGURE 21-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)358FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)35821.7 A/D Converter Calibration35921.8 Operation in Power-Managed Modes359EXAMPLE 21-1: Sample A/D Calibration Routine359TABLE 21-2: Summary of A/D Registers36022.0 Comparator Module36122.1 Registers361FIGURE 22-1: Comparator Simplified Block Diagram361Register 22-1: CMxCON: Comparator Control x Register (Access FD2h/FD1h)362Register 22-2: CMSTAT: Comparator Status Register (Access F70h)36322.2 Comparator Operation364FIGURE 22-2: Single Comparator36422.3 Comparator Response Time36422.4 Analog Input Connection Considerations364FIGURE 22-3: Comparator Analog Input Model36422.5 Comparator Control and Configuration365TABLE 22-1: Comparator Inputs and Outputs36522.5.1 Comparator Enable and Input selection36522.5.2 Comparator Enable and OUtput Selection365FIGURE 22-4: Comparator Configurations36622.6 Comparator Interrupts367TABLE 22-2: Comparator Interrupt Generation36722.7 Comparator Operation During Sleep36822.8 Effects of a Reset368TABLE 22-3: Registers Associated with Comparator Module36823.0 Comparator Voltage Reference Module369FIGURE 23-1: Comparator Voltage Reference Block Diagram36923.1 Configuring the Comparator Voltage Reference370EQUATION 23-1: Calculating Output of the Comparator Voltage Reference370Register 23-1: CVRCON: Comparator Voltage Reference Control Register (Banked F53h)37023.2 Voltage Reference Accuracy/Error37123.3 Connection Considerations37123.4 Operation During Sleep37123.5 Effects of a Reset371FIGURE 23-2: Comparator Voltage Reference Output Buffer Example371TABLE 23-1: Registers Associated with Comparator Voltage Reference37124.0 High/Low Voltage Detect (HLVD)373Register 24-1: HLVDCON: High/Low-Voltage Detect Control Register (Access F85h)37324.1 Operation374FIGURE 24-1: HLVD Module Block Diagram (with External Input)37424.2 HLVD Setup37524.3 Current Consumption37524.4 HLVD Start-up Time375FIGURE 24-2: Low-Voltage Detect Operation (VDIRMAG = 0)376FIGURE 24-3: High-Voltage Detect Operation (VDIRMAG = 1)37724.5 Applications377FIGURE 24-4: Typical High/ Low-Voltage Detect Application37724.6 Operation During Sleep37824.7 Effects of a Reset378TABLE 24-1: Registers Associated with High/Low-Voltage Detect Module37825.0 Charge Time Measurement Unit (CTMU)379FIGURE 25-1: CTMU Block Diagram37925.1 CTMU Operation38025.1.1 Theory of Operation38025.1.2 Current Source38025.1.3 Edge Selection and Control38025.1.4 Edge Status38025.1.5 Interrupts38125.2 CTMU Module Initialization38125.3 Calibrating the CTMU Module38125.3.1 Current Source Calibration381FIGURE 25-2: CTMU Current Source Calibration Circuit382EXAMPLE 25-1: Setup for CTMU Calibration Routines383EXAMPLE 25-2: Current Calibration Routine38425.3.2 Capacitance Calibration385EXAMPLE 25-3: Capacitance Calibration Routine38625.4 Measuring Capacitance with the CTMU38725.4.1 Absolute Capacitance Measurement38725.4.2 Relative Charge Measurement387EXAMPLE 25-4: Routine for Capacitive Touch Switch38825.5 Measuring Time with the CTMU Module389FIGURE 25-3: Typical Connections and Internal Configuration for Time Measurement38925.6 Creating a Delay with the CTMU Module390FIGURE 25-4: Typical Connections and Internal Configuration for Pulse Delay Generation39025.7 Operation During Sleep/Idle Modes39025.7.1 Sleep Mode and Deep Sleep Modes39025.7.2 Idle Mode39025.8 Effects of a Reset on CTMU39025.9 Registers391Register 25-1: CTMUCONH: CTMU Control Register High (Access FB3h)391Register 25-2: CTMUCONL: CTMU Control Register Low (Access FB2h)392Register 25-3: CTMUICON: CTMU current Control Register (Access FB1h)393TABLE 25-1: Registers Associated with CTMU Module39326.0 Special Features of the CPU39526.1 Configuration Bits39526.1.1 Considerations for Configuring the PIC18F46J11 family Devices395TABLE 26-1: Mapping of the Flash Configuration Words to the Configuration Registers396TABLE 26-2: Configuration Bits and Device IDs396Register 26-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)397Register 26-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)398Register 26-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)399Register 26-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)400Register 26-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)401Register 26-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)402Register 26-7: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)402Register 26-8: CONFIG4H: Configuration Register 4 High (Byte Address 300007h)403Register 26-9: DEVID1: Device ID Register 1 for PIC18F46J11 family Devices (Byte Address 3FFFFEh)403Register 26-10: DEVID2: Device ID Register 2 for PIC18F46J11 family Devices (Byte Address 3FFFFFh)40426.2 Watchdog Timer (WDT)40526.2.1 Control Register405FIGURE 26-1: WDT Block Diagram405Register 26-11: WDTCON: Watchdog Timer Control Register (Access FC0h)406TABLE 26-3: Summary of Watchdog Timer Registers40626.3 On-Chip Voltage Regulator40726.3.1 Voltage Regulator Tracking Mode And Low-Voltage Detection407FIGURE 26-2: Connections for the On-Chip Regulator40826.3.2 On-Chip Regulator and BOR40826.3.3 Power-up Requirements40826.3.4 OPERATION IN SLEEP MODE40826.4 Two-Speed Start-up409FIGURE 26-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)40926.4.1 Special Considerations for Using Two-Speed Start-up40926.5 Fail-Safe Clock Monitor409FIGURE 26-4: FSCM Block Diagram41026.5.1 FSCM and the Watchdog Timer410FIGURE 26-5: FSCM Timing Diagram41026.5.2 Exiting Fail-Safe Operation41126.5.3 FSCM Interrupts in Power-Managed Modes41126.5.4 POR or Wake-up From Sleep41126.6 Program Verification and Code Protection41126.6.1 Configuration Register Protection41126.7 In-Circuit Serial Programming (ICSP)41226.8 In-Circuit Debugger412TABLE 26-4: Debugger Resources41227.0 Instruction Set Summary41327.1 Standard Instruction Set413TABLE 27-1: Opcode Field Descriptions414EXAMPLE 27-1: General Format for Instructions415TABLE 27-2: PIC18F46J11 family Instruction Set41627.1.1 Standard Instruction Set41927.2 Extended Instruction Set45527.2.1 Extended Instruction Syntax455TABLE 27-3: Extensions to the PIC18 Instruction Set45527.2.2 Extended Instruction Set45627.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode46027.2.4 Considerations When Enabling the Extended Instruction Set46027.2.5 Special Considerations with Microchip MPLAB® IDE Tools46228.0 Development Support46328.1 MPLAB Integrated Development Environment Software46328.2 MPASM Assembler46428.3 MPLAB C18 and MPLAB C30 C Compilers46428.4 MPLINK Object Linker/ MPLIB Object Librarian46428.5 MPLAB ASM30 Assembler, Linker and Librarian46428.6 MPLAB SIM Software Simulator46428.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator46528.8 MPLAB REAL ICE In-Circuit Emulator System46528.9 MPLAB ICD 2 In-Circuit Debugger46528.10 MPLAB PM3 Device Programmer46528.11 PICSTART Plus Development Programmer46628.12 PICkit 2 Development Programmer46628.13 Demonstration, Development and Evaluation Boards46629.0 Electrical Characteristics467Absolute Maximum Ratings(†)467FIGURE 29-1: PIC18F46J11 family Vdd frequency Graph (Industrial)467FIGURE 29-2: PIC18LF46J11 Vddcore frequency Graph (Industrial)(1)46829.1 DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial)46929.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial)47029.3 DC Characteristics: PIC18F46J11 Family (Industrial)480TABLE 29-1: Memory Programming Requirements482TABLE 29-2: Comparator Specifications482TABLE 29-3: CTMU Current Source Specifications482TABLE 29-4: Voltage Reference Specifications482TABLE 29-5: Internal Voltage Regulator Specifications483TABLE 29-6: ULPWU Specifications483FIGURE 29-3: High/Low-Voltage Detect Characteristics484TABLE 29-7: High/Low-Voltage Detect Characteristics48429.4 AC (Timing) Characteristics48529.4.1 Timing Parameter Symbology48529.4.2 Timing Conditions486TABLE 29-8: Temperature and Voltage Specifications – AC486FIGURE 29-4: Load Conditions for Device Timing Specifications48629.4.3 Timing Diagrams and Specifications486FIGURE 29-5: External Clock Timing486TABLE 29-9: External Clock Timing Requirements487TABLE 29-10: PLL Clock Timing Specifications487TABLE 29-11: Internal RC Accuracy (INTOSC and INTRC Sources)487FIGURE 29-6: CLKO and I/O Timing488TABLE 29-12: CLKO and I/O Timing Requirements488FIGURE 29-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing489TABLE 29-13: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements489TABLE 29-14: Low-Power Wake-Up Time490FIGURE 29-8: Timer0 and Timer1 External Clock Timings491TABLE 29-15: Timer0 and Timer1 External Clock Requirements491FIGURE 29-9: Enhanced Capture/Compare/PWM Timings492TABLE 29-16: Enhanced Capture/Compare/PWM Requirements492FIGURE 29-10: Parallel Master Port Read Timing Diagram493TABLE 29-17: Parallel Master Port Read Timing Requirements493FIGURE 29-11: Parallel Master Port Write Timing Diagram494TABLE 29-18: Parallel Master Port Write Timing Requirements494FIGURE 29-12: Parallel Slave Port Timing495TABLE 29-19: Parallel Slave Port Requirements495FIGURE 29-13: Example SPI Master Mode Timing (CKE = 0)496TABLE 29-20: Example SPI Mode Requirements (Master Mode, Cke = 0)496FIGURE 29-14: Example SPI Master Mode Timing (CKE = 1)497TABLE 29-21: Example SPI Mode Requirements (Master Mode, CKE = 1)497FIGURE 29-15: Example SPI Slave Mode Timing (CKE = 0)498TABLE 29-22: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)498FIGURE 29-16: Example SPI Slave Mode Timing (CKE = 1)499TABLE 29-23: Example SPI Slave Mode Requirements (CKE = 1)499FIGURE 29-17: I2C™ Bus Start/Stop Bits Timing500TABLE 29-24: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)500FIGURE 29-18: I2C™ Bus Data Timing500TABLE 29-25: I2C™ Bus Data Requirements (Slave Mode)501FIGURE 29-19: MSSPx I2C™ Bus Start/Stop Bits Timing Waveforms502TABLE 29-26: MSSPx I2C™ Bus Start/Stop Bits Requirements502FIGURE 29-20: MSSPx I2C™ Bus Data Timing502TABLE 29-27: MSSPx I2C™ Bus Data Requirements503FIGURE 29-21: EUSARTx Synchronous Transmission (Master/Slave) Timing504TABLE 29-28: EUSARTx Synchronous Transmission Requirements504FIGURE 29-22: EUSARTx Synchronous Receive (Master/Slave) Timing504TABLE 29-29: EUSARTx Synchronous Receive Requirements504TABLE 29-30: A/D Converter Characteristics: PIC18F46J11 family (Industrial)505FIGURE 29-23: A/D Conversion Timing506TABLE 29-31: A/D Conversion Requirements50630.0 Packaging Information50730.1 Package Marking Information50730.2 Package Details509Appendix A: Revision History519Appendix B: Device Differences519TABLE B-1: DEVICE DIFFERENCES BETWEEN PIC18F46J11 family MEMBERS519INDEX521The Microchip Web Site533Customer Change Notification Service533Customer Support533Reader Response534Product Identification System535Worldwide Sales and Service536크기: 3.97메가바이트페이지: 536Language: English매뉴얼 열기