Microchip Technology MA240029 데이터 시트
PIC24FJ128GA310 FAMILY
DS39996F-page 252
2010-2011 Microchip Technology Inc.
REGISTER 19-3:
MDCAR: MODULATOR CARRIER CONTROL REGISTER
R/W-x
R/W-x
R/W-x
U-0
R/W-x
R/W-x
R/W-x
R/W-x
CHODIS
CHPOL
CHSYNC
—
CH3
CH2
(
CH1
(
)
CH0
(
)
bit 15
bit 8
R/W-0
R/W-x
R/W-x
U-0
R/W-x
R/W-x
R/W-x
R/W-x
CLODIS
CLPOL
CLSYNC
—
CL3
CL2
CL1
CL0
(
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHODIS:
Modulator High Carrier Output Disable bit
1
= Output signal driving the peripheral output pin (selected by CH<3:0>) is disabled
0
= Output signal driving the peripheral output pin is enabled
bit 14
CHPOL:
Modulator High Carrier Polarity Select bit
1
= Selected high carrier signal is inverted
0
= Selected high carrier signal is not inverted
bit 13
CHSYNC:
Modulator High Carrier Synchronization Enable bit
1
= Modulator waits for a falling edge on the high carrier before allowing a switch to the low carrier
0
= Modulator output is not synchronized to the high time carrier signal
bit 12
Unimplemented:
Read as ‘0’
bit 11-8
CH<3:0>
Modulator Data High Carrier Selection bits
1111
. . .
= Reserved
1011
1010
= Output Compare/PWM Module 7 output
1001
= Output Compare/PWM Module 6 output
1000
= Output Compare/PWM Module 5 output
0111
= Output Compare/PWM Module 4 output
0110
= Output Compare/PWM Module 3 output
0101
= Output Compare/PWM Module 2 output
0100
= Output Compare/PWM Module 1 output
0011
= Reference clock (REFO) output
0010
= Input on MDCIN2 pin
0001
= Input on MDCIN1 pin
0000
= V
SS
bit 7
CLODIS:
Modulator Low Carrier Output Disable bit
1
= Output signal driving the peripheral output pin (selected by CL<3:0>) is disabled
0
= Output signal driving the peripheral output pin is enabled
bit 6
CLPOL:
Modulator Low Carrier Polarity Select bit
1
= Selected low carrier signal is inverted
0
= Selected low carrier signal is not inverted
bit 5
CLSYNC:
Modulator Low Carrier Synchronization Enable bit
1
= Modulator waits for a falling edge on the low carrier before allowing a switch to the high carrier
0
= Modulator output is not synchronized to the low time carrier signal
(
)
bit 4
Unimplemented:
Read as ‘0’
bit 3-0
CL<3:0>
Modulator Data Low Carrier Selection bits
(
)
Bit settings are identical to those for CH<3:0>.
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.