데이터 시트차례Extreme Low-Power Features:1Peripheral Features:1Peripheral Features (continued):1Analog Features:1High-Performance CPU:2Special Microcontroller Features:2Pin Diagrams3Pin Diagrams (continued)4Pin Diagrams (continued)5Pin Diagrams (continued)6Table of Contents9Most Current Data Sheet10Errata10Customer Notification System101.0 Device Overview111.1 Core Features111.1.1 16-Bit Architecture111.1.2 nanoWatt XLP Power-Saving Technology111.1.3 Oscillator Options and Features111.1.4 Easy Migration111.2 DMA Controller121.3 LCD Controller121.4 Other Special Features121.5 Details on Individual Family Members12TABLE 1-1: Device Features for the PIC24FJ128GA310 family: 64-pin13TABLE 1-2: Device Features for the PIC24FJ128GA310 family: 80-pin14TABLE 1-3: Device Features for the PIC24FJ128GA310 family: 100-pin Devices15FIGURE 1-1: PIC24FJ128GA310 family General Block Diagram16TABLE 1-4: PIC24FJ128GA310 family Pinout Descriptions172.0 Guidelines for Getting Started with 16-bit Microcontrollers292.1 Basic Connection Requirements29FIGURE 2-1: Recommended Minimum connections292.2 Power Supply Pins302.2.1 Decoupling Capacitors302.2.2 Tank Capacitors302.3 Master Clear (MCLR) Pin30FIGURE 2-2: Example of MCLR Pin Connections302.4 Voltage Regulator Pin (Vcap)31FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap31TABLE 2-1: Suitable Capacitor Equivalents312.4.1 Considerations for Ceramic Capacitors32FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics322.5 ICSP Pins322.6 External Oscillator Pins33FIGURE 2-5: Suggested Placement of the Oscillator Circuit332.7 Configuration of Analog and Digital Pins During ICSP Operations342.8 Unused I/Os343.0 CPU353.1 Programmer’s Model35FIGURE 3-1: PIC24F CPU Core Block Diagram36TABLE 3-1: CPU Core Registers36FIGURE 3-2: Programmer’s Model373.2 CPU Control Registers38Register 3-1: SR: ALU STATUS Register38Register 3-2: CORCON: CPU Core Control Register393.3 Arithmetic Logic Unit (ALU)403.3.1 Multiplier403.3.2 Divider403.3.3 Multi-Bit Shift Support40TABLE 3-2: Instructions that Use the Single Bit and Multi-Bit Shift Operation404.0 Memory Organization414.1 Program Memory Space41FIGURE 4-1: Program Space Memory Map for PIC24FJ128GA310 family Devices414.1.1 Program Memory Organization424.1.2 Hard Memory Vectors424.1.3 Flash Configuration Words42TABLE 4-1: Flash Configuration Words for PIC24FJ128GA310 family Devices42FIGURE 4-2: Program Memory Organization424.2 Data Memory Space434.2.1 Data Space Width43FIGURE 4-3: Data Space Memory Map for PIC24FJ128GA310 family Devices434.2.2 Data Memory Organization and Alignment444.2.3 Near Data Space444.2.4 Special Function Register (SFR) Space44TABLE 4-2: Implemented Regions of SFR Data Space44TABLE 4-3: CPU CORE Registers Map45TABLE 4-4: ICN Register Map46TABLE 4-5: Interrupt Controller Register Map47TABLE 4-6: Timer Register Map48TABLE 4-7: Input Capture Register Map49TABLE 4-8: Output Compare Register Map50TABLE 4-9: I2C™ Register Map51TABLE 4-10: UART Register Maps52TABLE 4-11: SPI Register Map53TABLE 4-12: PORTA Register Map(1)53TABLE 4-13: PORTb Register Map53TABLE 4-14: PORTC Register Map54TABLE 4-15: PORTD Register Map54TABLE 4-16: PORTE Register Map54TABLE 4-17: PORTF Register Map55TABLE 4-18: PORTG Register Map55TABLE 4-19: Pad Configuration Register Map (PADCFG1)55TABLE 4-20: A/D Register Map56TABLE 4-21: CTMU Register Map57TABLE 4-22: Analog Configuration Register Map57TABLE 4-23: DMA Register Map58TABLE 4-24: LCD Register Map59TABLE 4-25: Parallel Master/Slave Port Register Map60TABLE 4-26: Real-Time Clock and Calendar (RTCC) Register Map61TABLE 4-27: Data Signal Modulator (DSM) Register Map61TABLE 4-28: Comparators Register Map61TABLE 4-29: CRC Register Map62TABLE 4-30: Peripheral Pin Select Register Map62TABLE 4-31: System Control (Clock and Reset) Register Map63TABLE 4-32: Deep Sleep Register Map64TABLE 4-33: NVM Register Map64TABLE 4-34: PMD Register Map644.2.5 Extended Data Space (EDS)65TABLE 4-35: Total Accessible Data Memory65FIGURE 4-4: Extended Data Space65FIGURE 4-5: EDS Address Generation for Read Operations66EXAMPLE 4-1: EDS Read Code In Assembly66FIGURE 4-6: EDS Address Generation for Write Operations67EXAMPLE 4-2: EDS Write Code In Assembly67TABLE 4-36: EDS Memory Address with Different Pages and Addresses684.2.6 Software Stack68FIGURE 4-7: CALL Stack Frame684.3 Interfacing Program and Data Memory Spaces694.3.1 Addressing Program Space69TABLE 4-37: Program Space Address Construction69FIGURE 4-8: Data Access from Program Space Address Generation704.3.2 Data Access from Program Memory Using Table Instructions71FIGURE 4-9: Accessing Program Memory with Table Instructions714.3.3 Reading Data from Program Memory Using EDS72TABLE 4-38: EDS Program Address with different Pages and Addresses72EXAMPLE 4-3: EDS Read Code from Program Memory In Assembly72FIGURE 4-10: Program Space Visibility Operation to Access Lower Word73FIGURE 4-11: Program Space Visibility Operation to Access Upper Word735.0 Direct Memory Access Controller (DMA)75FIGURE 5-1: DMA Functional Block Diagram755.1 Summary of DMA Operations765.1.1 Source and Destination765.1.2 Data Size765.1.3 Trigger Source765.1.4 Transfer Mode765.1.5 Addressing Modes76FIGURE 5-2: Types of DMA Data Transfers775.1.6 Channel Priority785.2 Typical Setup785.3 Peripheral Module Disable785.4 Registers78Register 5-1: DMACON: DMA Engine Control Register79Register 5-2: DMACHn: DMA CHannel n Control Register80Register 5-3: DMAINTn: DMA Channel n Interrupt Register81TABLE 5-1: DMA Trigger Sources826.0 Flash Program Memory836.1 Table Instructions and Flash Programming83FIGURE 6-1: Addressing for Table Registers836.2 RTSP Operation846.3 JTAG Operation846.4 Enhanced In-Circuit Serial Programming846.5 Control Registers846.6 Programming Operations84Register 6-1: NVMCON: Flash Memory Control Register856.6.1 Programming Algorithm for Flash Program Memory86EXAMPLE 6-1: Erasing a Program Memory Block (Assembly Language Code)86EXAMPLE 6-2: Erasing a Program Memory Block (‘C’ Language Code)87EXAMPLE 6-3: LOADING THE WRITE BUFFERS87EXAMPLE 6-4: Initiating a Programming Sequence876.6.2 Programming a single word of flash program memory88EXAMPLE 6-5: Programming a Single Word of Flash Program Memory88EXAMPLE 6-6: Programming a Single Word of Flash Program Memory (‘C’ Language Code)887.0 Resets89FIGURE 7-1: Reset System Block Diagram89Register 7-1: RCON: Reset Control Register90Register 7-2: RCON2: Reset and System Control Register 292TABLE 7-1: Reset Flag Bit Operation937.1 Special Function Register Reset States937.2 Device Reset Times937.3 Brown-out Reset (BOR)937.4 Clock Source Selection at Reset93TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)93TABLE 7-3: Reset Delay Times for Various Device Resets947.4.1 POR and Long Oscillator Start-up Times947.4.2 Fail-Safe Clock Monitor (FSCM) and Device Resets948.0 Interrupt Controller958.1 Interrupt Vector Table958.1.1 Alternate Interrupt Vector Table958.2 Reset Sequence95FIGURE 8-1: PIC24F Interrupt Vector Table96TABLE 8-1: Trap Vector Details96TABLE 8-2: Implemented Interrupt Vectors978.3 Interrupt Control and Status Registers98Register 8-1: SR: ALU STATUS Register (in CPU)99Register 8-2: CORCON: CPU Control Register100Register 8-3: INTCON1: Interrupt Control Register 1101Register 8-4: INTCON2: Interrupt Control Register 2102Register 8-5: IFS0: Interrupt Flag Status Register 0103Register 8-6: IFS1: Interrupt Flag Status Register 1105Register 8-7: IFS2: Interrupt Flag Status Register 2107Register 8-8: IFS3: Interrupt Flag Status Register 3108Register 8-9: IFS4: Interrupt Flag Status Register 4109Register 8-10: IFS5: Interrupt Flag Status Register 5110Register 8-11: IFS6: Interrupt Flag Status Register 6111Register 8-12: IFS7: Interrupt Flag Status Register 7111Register 8-13: IEC0: Interrupt Enable Control Register 0112Register 8-14: IEC1: Interrupt Enable Control Register 1114Register 8-15: IEC2: Interrupt Enable Control Register 2116Register 8-16: IEC3: Interrupt Enable Control Register 3117Register 8-17: IEC4: Interrupt Enable Control Register 4118Register 8-18: IEC5: Interrupt Enable Control Register 5119Register 8-19: IEC6: Interrupt Enable Control Register 6120Register 8-20: IEC7: Interrupt Enable Control Register 7120Register 8-21: IPC0: Interrupt Priority Control Register 0121Register 8-22: IPC1: Interrupt Priority Control Register 1122Register 8-23: IPC2: Interrupt Priority Control Register 2123Register 8-24: IPC3: Interrupt Priority Control Register 3124Register 8-25: IPC4: Interrupt Priority Control Register 4125Register 8-26: IPC5: Interrupt Priority Control Register 5126Register 8-27: IPC6: Interrupt Priority Control Register 6127Register 8-28: IPC7: Interrupt Priority Control Register 7128Register 8-29: IPC8: Interrupt Priority Control Register 8129Register 8-30: IPC9: Interrupt Priority Control Register 9130Register 8-31: IPC10: Interrupt Priority Control Register 10131Register 8-32: IPC11: Interrupt Priority Control Register 11132Register 8-33: IPC12: Interrupt Priority Control Register 12133Register 8-34: IPC13: Interrupt Priority Control Register 13134Register 8-35: IPC15: Interrupt Priority Control Register 15135Register 8-36: IPC16: Interrupt Priority Control Register 16136Register 8-37: IPC18: Interrupt Priority Control Register 18137Register 8-38: IPC19: Interrupt Priority Control Register 19137Register 8-39: IPC20: Interrupt Priority Control Register 20138Register 8-40: IPC21: Interrupt Priority Control Register 21139Register 8-41: IPC22: Interrupt Priority Control Register 22140Register 8-42: IPC25: Interrupt Priority Control Register 25141Register 8-43: IPC29: Interrupt Priority Control Register 29141Register 8-44: INTTREG: Interrupt Controller Test Register1428.4 Interrupt Setup Procedures1438.4.1 Initialization1438.4.2 Interrupt Service Routine (ISR)1438.4.3 Trap Service Routine (TSR)1438.4.4 Interrupt Disable1439.0 Oscillator Configuration145FIGURE 9-1: PIC24FJ128GA310 family Clock Diagram1459.1 CPU Clocking Scheme1469.2 Initial Configuration on POR1469.2.1 Clock Switching Mode Configuration Bits146TABLE 9-1: Configuration Bit Values for Clock Selection1469.3 Control Registers147Register 9-1: OSCCON: Oscillator Control Register147Register 9-2: CLKDIV: Clock Divider Register149Register 9-3: OSCTUN: FRC Oscillator Tune Register1509.4 Clock Switching Operation1509.4.1 Enabling Clock Switching1509.4.2 Oscillator Switching Sequence151EXAMPLE 9-1: Basic Code Sequence for Clock Switching1519.5 Secondary Oscillator (SOSC)1529.5.1 Basic SOSC Operation1529.5.2 LOW-POWER SOSC OPERATION1529.5.3 External (Digital) Clock Mode (SCLKI)1529.5.4 SOSC LAYOUT Considerations1529.6 Reference Clock Output152Register 9-4: REFOCON: Reference Oscillator Control Register15310.0 Power-Saving Features15510.1 Overview of Power-Saving Modes155TABLE 10-1: Operating Modes for PIC24FJ128GA310 family Devices155TABLE 10-2: Exiting Power Saving Modes15610.1.1 Instruction-Based Power-Saving Modes156EXAMPLE 10-1: PWRSAV Instruction Syntax15610.1.2 Hardware-Based Power-Saving Mode15710.1.3 Low-Voltage/Retention Regulator15710.2 Idle Mode15710.3 Sleep Mode15710.3.1 Low-Voltage/Retention Sleep Mode15710.4 Deep Sleep Mode15810.4.1 Entering Deep Sleep Mode158EXAMPLE 10-2: The Repeat Sequence15810.4.2 Exiting Deep Sleep Modes15910.4.3 Saving Context Data with the DSGPRn Registers15910.4.4 I/O Pins in Deep Sleep Modes15910.4.5 Deep Sleep WDT16010.4.6 Checking and Clearing the Status of Deep Sleep16010.4.7 Power-on Resets (PORs)16010.5 Vbat Mode16010.5.1 Vbat mode with no RTCC16110.5.2 WAKE-UP FROM Vbat modes16110.5.3 I/O PINS DURING Vbat modes16110.5.4 Saving Context Data with the DSGPRn Registers161Register 10-1: DSCON: Deep Sleep Control Register(1)162Register 10-2: DSWAKE: Deep Sleep Wake-Up Source Register(1)163Register 10-3: RCON2: Reset and System Control Register 216410.6 Clock Frequency and Clock Switching16510.7 Doze Mode16510.8 Selective Peripheral Module Control16511.0 I/O Ports16711.1 Parallel I/O (PIO) Ports167FIGURE 11-1: Block Diagram of a Typical Shared Port Structure16711.1.1 I/O Port Write/Read Timing16811.1.2 Open-Drain Configuration16811.2 Configuring Analog Port Pins (ANSx)16811.2.1 Analog Input Pins and Voltage Considerations168TABLE 11-1: Configuring Analog/Digital Function of an I/O Pin168TABLE 11-2: Input Voltage Levels for Port or Pin Tolerated Description Input168Register 11-1: ANSA: PortA Analog Function Selection Register169Register 11-2: ANSB: PortB Analog Function Selection Register169Register 11-3: ANSC: PortC Analog Function Selection Register170Register 11-4: ANSD: PortD Analog Function Selection Register170Register 11-5: ANSE: PortE Analog Function Selection Register(1)171Register 11-6: ANSG: PortG Analog Function Selection Register17111.3 Input Change Notification172EXAMPLE 11-1: Port Write/Read in Assembly172EXAMPLE 11-2: Port Write/Read in ‘C’17211.4 Peripheral Pin Select (PPS)17311.4.1 Available Pins17311.4.2 Available Peripherals17311.4.3 Controlling Peripheral Pin Select173TABLE 11-3: Selectable Input Sources (Maps Input to Function)(1)174TABLE 11-4: Selectable Output Sources (Maps Function to Output)17511.4.4 Controlling Configuration Changes176TABLE 11-5: Remappable Pin Exceptions for PIC24FJ128GA310 family Devices17611.4.5 Considerations for Peripheral Pin Selection177EXAMPLE 11-3: Configuring UART1 Input and Output Functions17711.4.6 Peripheral Pin Select Registers178Register 11-7: RPINR0: Peripheral Pin Select Input Register 0178Register 11-8: RPINR1: Peripheral Pin Select Input Register 1178Register 11-9: RPINR2: Peripheral Pin Select Input Register 2179Register 11-10: RPINR3: Peripheral Pin Select Input Register 3179Register 11-11: RPINR4: Peripheral Pin Select Input Register 4180Register 11-12: RPINR7: Peripheral Pin Select Input Register 7180Register 11-13: RPINR8: Peripheral Pin Select Input Register 8181Register 11-14: RPINR9: Peripheral Pin Select Input Register 9181Register 11-15: RPINR10: Peripheral Pin Select Input Register 10182Register 11-16: RPINR11: Peripheral Pin Select Input Register 11182Register 11-17: RPINR17: Peripheral Pin Select Input Register 17183Register 11-18: RPINR18: Peripheral Pin Select Input Register 18183Register 11-19: RPINR19: Peripheral Pin Select Input Register 19184Register 11-20: RPINR20: Peripheral Pin Select Input Register 20184Register 11-21: RPINR21: Peripheral Pin Select Input Register 21185Register 11-22: RPINR22: Peripheral Pin Select Input Register 22185Register 11-23: RPINR23: Peripheral Pin Select Input Register 23186Register 11-24: RPINR27: Peripheral Pin Select Input Register 27186Register 11-25: RPINR30: Peripheral Pin Select Input Register 30187Register 11-26: RPINR31: Peripheral Pin Select Input Register 31187Register 11-27: RPOR0: Peripheral Pin Select Output Register 0188Register 11-28: RPOR1: Peripheral Pin Select Output Register 1188Register 11-29: RPOR2: Peripheral Pin Select Output Register 2189Register 11-30: RPOR3: Peripheral Pin Select Output Register 3189Register 11-31: RPOR4: Peripheral Pin Select Output Register 4190Register 11-32: RPOR5: Peripheral Pin Select Output Register 5190Register 11-33: RPOR6: Peripheral Pin Select Output Register 6191Register 11-34: RPOR7: Peripheral Pin Select Output Register 7191Register 11-35: RPOR8: Peripheral Pin Select Output Register 8192Register 11-36: RPOR9: Peripheral Pin Select Output Register 9192Register 11-37: RPOR10: Peripheral Pin Select Output Register 10193Register 11-38: RPOR11: Peripheral Pin Select Output Register 11193Register 11-39: RPOR12: Peripheral Pin Select Output Register 12194Register 11-40: RPOR13: Peripheral Pin Select Output Register 13194Register 11-41: RPOR14: Peripheral Pin Select Output Register 14195Register 11-42: RPOR15: Peripheral Pin Select Output Register 1519512.0 Timer1197FIGURE 12-1: 16-bit Timer1 Module Block Diagram197Register 12-1: T1CON: Timer1 Control Register(1)19813.0 Timer2/3 and Timer4/5199FIGURE 13-1: Timer2/3 and Timer4/5 (32-bit) Block Diagram200FIGURE 13-2: Timer2 and Timer4 (16-bit Synchronous) Block Diagram201FIGURE 13-3: Timer3 and Timer5 (16-bit Asynchronous) Block Diagram201Register 13-1: TxCON: Timer2 and Timer4 Control Register(3)202Register 13-2: TyCON: Timer3 and Timer5 Control Register(3)20314.0 Input Capture with Dedicated Timers20514.1 General Operating Modes20514.1.1 Synchronous and Trigger modes205FIGURE 14-1: Input Capture Block Diagram20514.1.2 Cascaded (32-bit) Mode20614.2 Capture Operations206Register 14-1: ICxCON1: Input Capture x Control Register 1207Register 14-2: ICxCON2: Input Capture x Control Register 220815.0 Output Compare with Dedicated Timers21115.1 General Operating Modes21115.1.1 Synchronous and Trigger modes21115.1.2 Cascaded (32-bit) Mode211FIGURE 15-1: Output Compare Block Diagram (16-bit Mode)21215.2 Compare Operations21215.3 Pulse-Width Modulation (PWM) Mode213FIGURE 15-2: Output Compare Block Diagram (Double-Buffered, 16-bit PWM Mode)21415.3.1 PWM Period214EQUATION 15-1: Calculating the PWM Period(1)21415.3.2 PWM Duty Cycle215EQUATION 15-2: Calculation for Maximum PWM Resolution(1)215EXAMPLE 15-1: PWM Period and Duty Cycle Calculations(1)215TABLE 15-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)(1)215TABLE 15-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)(1)215Register 15-1: OCxCON1: Output Compare x Control Register 1216Register 15-2: OCxCON2: Output Compare x Control Register 221816.0 Serial Peripheral Interface (SPI)221FIGURE 16-1: SPIx Module Block Diagram (Standard Mode)222FIGURE 16-2: SPIx Module Block Diagram (Enhanced Mode)223Register 16-1: SPIxSTAT: SPIx Status and Control Register224Register 16-2: SPIxCON1: SPIx Control Register 1226Register 16-3: SPIxCON2: SPIx Control Register 2228FIGURE 16-3: SPI Master/Slave Connection (Standard Mode)229FIGURE 16-4: SPI Master/Slave Connection (Enhanced Buffer Modes)229FIGURE 16-5: SPI Master, Frame Master Connection Diagram230FIGURE 16-6: SPI Master, Frame Slave Connection Diagram230FIGURE 16-7: SPI Slave, Frame Master Connection Diagram230FIGURE 16-8: SPI Slave, Frame Slave Connection Diagram230EQUATION 16-1: Relationship Between Device and SPI Clock Speed(1)231TABLE 16-1: Sample SCKx Frequencies(1,2)23117.0 Inter-Integrated Circuit™ (I2C™)23317.1 Communicating as a Master in a Single Master Environment233FIGURE 17-1: I2C™ Block Diagram23417.2 Setting Baud Rate When Operating as a Bus Master235EQUATION 17-1: Computing Baud Rate Reload Value(1,2)23517.3 Slave Address Masking235TABLE 17-1: I2C™ Clock Rates(1,2)235TABLE 17-2: I2C™ reserved addresses(1)235Register 17-1: I2CxCON: I2Cx Control Register236Register 17-2: I2CxSTAT: I2Cx Status Register238Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register23918.0 Universal Asynchronous Receiver Transmitter (UART)241FIGURE 18-1: UART Simplified Block Diagram24118.1 UART Baud Rate Generator (BRG)242EQUATION 18-1: UART Baud Rate with BRGH = 0(1,2)242EQUATION 18-2: UART Baud Rate with BRGH = 1(1,2)242EXAMPLE 18-1: Baud Rate Error Calculation (BRGH = 0)(1)24218.2 Transmitting in 8-Bit Data Mode24318.3 Transmitting in 9-Bit Data Mode24318.4 Break and Sync Transmit Sequence24318.5 Receiving in 8-Bit or 9-Bit Data Mode24318.6 Operation of UxCTS and UxRTS Control Pins24318.7 Infrared Support24318.7.1 IrDA Clock Output for External IrDA Support24318.7.2 Built-in IrDA Encoder and Decoder243Register 18-1: UxMODE: UARTx Mode Register244Register 18-2: UxSTA: UARTx Status and Control Register24619.0 Data Signal Modulator249FIGURE 19-1: Simplified Block Diagram of the Data SIgnal Modulator249Register 19-1: MDCON: Modulator Control Register250Register 19-2: MDSRC: Modulator Source Control Register251Register 19-3: MDCAR: Modulator Carrier Control Register25220.0 Enhanced Parallel Master Port (EPMP)25320.1 Specific Package Variations253TABLE 20-1: EPMP Feature Differences By Device Pin Count253TABLE 20-2: Enhanced Parallel Master Port Pin Descriptions254Register 20-1: PMCON1: EPMP Control Register 1255Register 20-2: PMCON2: EPMP Control Register 2256Register 20-3: PMCON3: EPMP Control Register 3257Register 20-4: PMCON4: EPMP Control Register 4258Register 20-5: PMCSxCF: Chip Select x Configuration Register259Register 20-6: PMCSxBS: Chip Select x Base Address Register(2)260Register 20-7: PMCSxMD: Chip Select x Mode Register261Register 20-8: PMSTAT: EPMP Status Register (Slave mode only)262Register 20-9: PADCFG1: Pad Configuration Control Register26321.0 Liquid Crystal Display (LCD) Controller265FIGURE 21-1: LCD Controller Module Block Diagram26521.1 Registers266Register 21-1: LCDCON: LCD Control Register266Register 21-2: LCDREG: LCD Charge Pump Control Register268Register 21-3: LCDPS: LCD Phase Register269Register 21-4: LCDSEx: LCD SEGMENT x Enable Register270Register 21-5: LCDDATAx: LCD DATA x Register270TABLE 21-1: LCDDATA Registers And Bits For Segment And COM Combinations271Register 21-6: LCDREF: LCD Reference Ladder Control Register27222.0 Real-Time Clock and Calendar (RTCC)27522.1 RTCC Source Clock275FIGURE 22-1: RTCC Block Diagram27522.2 RTCC Module Registers27622.2.1 Register Mapping276TABLE 22-1: RTCVAL Register Mapping276TABLE 22-2: ALRMVAL Register Mapping27622.2.2 Write Lock27622.2.3 Selecting RTCC Clock Source276EXAMPLE 22-1: Setting the RTCWREN Bit27622.3 Registers27722.3.1 RTCC Control Registers277Register 22-1: RCFGCAL: RTCC Calibration/Configuration Register(1)277Register 22-2: RTCPWC: RTCC Power Control Register(1)279Register 22-3: ALCFGRPT: Alarm Configuration Register28022.3.2 RTCVAL Register Mappings281Register 22-4: YEAR: Year Value Register(1)281Register 22-5: MTHDY: Month and Day Value Register(1)281Register 22-6: WKDYHR: Weekday and Hours Value Register(1)282Register 22-7: MINSEC: Minutes and Seconds Value Register28222.3.3 ALRMVAL Register Mappings283Register 22-8: ALMTHDY: Alarm Month and Day Value Register(1)283Register 22-9: ALWDHR: Alarm Weekday and Hours Value Register(1)283Register 22-10: ALMINSEC: Alarm Minutes and Seconds Value Register284Register 22-11: RTCCSWT: Power Control and Sample Window Timer Register(1)28522.4 Calibration286EQUATION 22-1:28622.5 Alarm28622.5.1 Configuring The Alarm28622.5.2 Alarm Interrupt286FIGURE 22-2: Alarm Mask Settings28722.6 POWER CONTROL28722.7 RTCC Vbat OPERATION28723.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator289FIGURE 23-1: CRC Block Diagram289FIGURE 23-2: CRC Shift Engine Detail28923.1 User Interface29023.1.1 Polynomial Interface290EQUATION 23-1: 16-Bit, 32-bit CRC Polynomials29023.1.2 DATA INTERFACE290TABLE 23-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALs29023.1.3 Data Shift Direction29123.1.4 Interrupt Operation29123.1.5 Typical Operation291Register 23-1: CRCCON1: CRC Control 1 Register292Register 23-2: CRCCON2: CRC Control 2 Register293Register 23-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE293Register 23-4: CRCXORH: CRC XOR High Register29424.0 12-Bit A/D Converter with Threshold Scan29524.1 Basic Operation295FIGURE 24-1: 12-Bit A/D Converter Block Diagram (PIC24FJ128GA310 family)29624.2 Extended DMA Operations29724.2.1 Extended Buffer Mode29724.2.2 PIA Mode29724.3 A/D Operation with Vbat29724.4 Registers298TABLE 24-1: Indirect Address Generation in PIA Mode298FIGURE 24-2: Example of Buffer Address Generation in PIA Mode (4-Word Buffers Per Channel)299Register 24-1: AD1CON1: A/D Control Register 1300Register 24-2: AD1CON2: A/D Control Register 2302Register 24-3: AD1CON3: A/D Control Register 3303Register 24-4: AD1CON4: A/D control register 4304Register 24-5: AD1CON5: A/D Control Register 5305Register 24-6: AD1CHS: A/D Sample Select Register306Register 24-7: ANCFG: A/D Band Gap rEFERENCE cONFIGURATION307Register 24-8: AD1CHITH: A/D Scan Compare Hit Register (High Word)308Register 24-9: AD1CHITL: A/D Scan Compare Hit Register (Low Word)308Register 24-10: AD1CSSH: A/D Input Scan Select Register (High Word)309Register 24-11: AD1CSSL: A/D Input Scan Select Register (Low word)309Register 24-12: AD1CTMENH: CTMU Enable Register (High Word)(1)310Register 24-13: AD1CTMENL: CTMU Enable Register (Low Word)(1)310FIGURE 24-3: 10-Bit A/D Converter Analog Input Model311EQUATION 24-1: A/D Conversion Clock Period311FIGURE 24-4: 12-bit A/D Transfer Function312FIGURE 24-5: 10-bit A/D Transfer Function31325.0 Triple Comparator Module315FIGURE 25-1: Triple Comparator Module Block Diagram315FIGURE 25-2: Individual Comparator Configurations when CREF = 0316FIGURE 25-3: Individual Comparator Configurations when CREF = 1 and CVREFP = 0317FIGURE 25-4: Individual Comparator Configurations when CREF = 1 and CVREFP = 1317Register 25-1: CMxCON: Comparator x Control Registers (Comparators 1 Through 3)318Register 25-2: CMSTAT: Comparator Module Status Register31926.0 Comparator Voltage Reference32126.1 Configuring the Comparator Voltage Reference321FIGURE 26-1: Comparator Voltage Reference Block Diagram321Register 26-1: CVRCON: Comparator Voltage Reference Control Register32227.0 Charge Time Measurement Unit (CTMU)32327.1 Measuring Capacitance323EQUATION 27-1:323FIGURE 27-1: Typical Connections and Internal Configuration for Capacitance Measurement32427.2 Measuring Time32427.3 Pulse Generation and Delay324FIGURE 27-2: Typical Connections and Internal Configuration for Time Measurement325FIGURE 27-3: Typical Connections and Internal Configuration for Pulse Delay Generation325Register 27-1: CTMUCON1: CTMU Control Register 1326Register 27-2: CTMUCON2: CTMU ControL Register 2327Register 27-3: CTMUICON: CTMU current Control Register32928.0 High/Low-Voltage Detect (HLVD)331FIGURE 28-1: High/Low-Voltage Detect (HLVD) Module Block Diagram331Register 28-1: HLVDCON: High/Low-Voltage Detect Control Register33229.0 Special Features33329.1 Configuration Bits33329.1.1 Considerations for Configuring PIC24FJ128GA310 family Devices333TABLE 29-1: Flash Configuration Word Locations for PIC24FJ128GA310 family Devices333Register 29-1: CW1: Flash Configuration Word 1334Register 29-2: CW2: Flash Configuration Word 2336Register 29-3: CW3: Flash Configuration Word 3338Register 29-4: CW4: Flash Configuration Word 4340Register 29-5: DEVID: Device ID Register342Register 29-6: DEVREV: Device Revision Register34229.2 On-Chip Voltage Regulator343FIGURE 29-1: Connections for the On-Chip Regulator34329.2.1 On-Chip Regulator and POR34329.2.2 Voltage Regulator Standby Mode34329.2.3 Low-Voltage/Retention Regulator34329.3 Watchdog Timer (WDT)34429.3.1 Windowed Operation34429.3.2 Control Register344FIGURE 29-2: WDT Block Diagram34429.4 Program Verification and Code Protection34529.4.1 General Segment Protection34529.4.2 Code Segment Protection345TABLE 29-2: Code Segment Protection Configuration Options34529.4.3 Configuration Register Protection34629.5 JTAG Interface34629.6 In-Circuit Serial Programming34629.7 In-Circuit Debugger34630.0 Development Support34731.0 Instruction Set Summary351TABLE 31-1: Symbols Used in Opcode Descriptions352TABLE 31-2: Instruction Set Overview35332.0 Electrical Characteristics359Absolute Maximum Ratings(†)35932.1 DC Characteristics360FIGURE 32-1: PIC24FJ128GA310 family Voltage-Frequency Graph (Industrial)360TABLE 32-1: Thermal Operating Conditions360TABLE 32-2: Thermal Packaging Characteristics360TABLE 32-3: DC Characteristics: Temperature and Voltage Specifications361TABLE 32-4: DC Characteristics: Operating Current (Idd)361TABLE 32-5: DC Characteristics: Idle Current (Iidle)362TABLE 32-6: DC Characteristics: Power-Down Current (Ipd)363TABLE 32-7: DC Characteristics: DCurrent (BOR, WDT, DSBOR, DSWDT, LCD)364TABLE 32-8: DC Characteristics: I/O Pin Input Specifications365TABLE 32-9: DC Characteristics: I/O Pin Output Specifications366TABLE 32-10: DC Characteristics: Program Memory366TABLE 32-11: Internal Voltage Regulator Specifications367TABLE 32-12: Vbat Operating Voltage Specifications367TABLE 32-13: CTMU Current Source Specifications367TABLE 32-14: High/Low-Voltage Detect Characteristics368TABLE 32-15: Comparator DC Specifications368TABLE 32-16: Comparator Voltage Reference DC Specifications36832.2 AC Characteristics and Timing Parameters369TABLE 32-17: Temperature and Voltage Specifications – AC369FIGURE 32-2: Load Conditions for Device Timing Specifications369TABLE 32-18: Capacitive Loading Requirements on Output Pins369FIGURE 32-3: External Clock Timing370TABLE 32-19: External Clock Timing Requirements370TABLE 32-20: PLL Clock Timing Specifications (Vdd = 2.2V to 3.6V)371TABLE 32-21: Internal RC Accuracy371TABLE 32-22: RC Oscillator Start-Up Time371FIGURE 32-4: CLKO and I/O Timing Characteristics372TABLE 32-23: CLKO and I/O Timing Requirements372TABLE 32-24: Reset and Brown-out Reset Requirements373TABLE 32-25: A/D Module Specifications374TABLE 32-26: A/D Conversion Timing Requirements(1)37533.0 Packaging Information37733.1 Package Marking Information37733.2 Package Marking Information37833.3 Package Details379Appendix A: Revision History393Revision A (March 2010)393Revision B (May 2011)393Revision C (July 2011)393Revision D (August 2011)393Revision E (October 2011)393Revision F (November 2011)393INDEX395The Microchip Web Site401Customer Change Notification Service401Customer Support401Reader Response402Product Identification System403Worldwide Sales and Service406크기: 3.09메가바이트페이지: 406Language: English매뉴얼 열기