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DS39996F-page 343

PIC24FJ128GA310 FAMILY

29.2

On-Chip Voltage Regulator

All PIC24FJ128GA310 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GA310 family
incorporate an on-chip regulator that allows the device
to run its core logic from V

This regulator is always enabled. It provides a constant
voltage (1.8V nominal) to the digital core logic, from a
V

of about 2.1V all the way up to the device’s V

MAX

. It does not have the capability to boost V

levels.

In order to prevent “brown-out” conditions when the
voltage drops too low for the regulator, the Brown-out
Reset occurs. Then the regulator output follows V

with a typical voltage drop of 300 mV.
A low-ESR capacitor (such as ceramic) must be
connected to the V

CAP

pin (

Figure 29-1

). This helps to

maintain the stability of the regulator. The recommended
value for the filter capacitor (C

EFC

) is provided in

Section 32.1 “DC Characteristics”

FIGURE 29-1:

CONNECTIONS FOR THE
ON-CHIP REGULATOR

29.2.1

ON-CHIP REGULATOR AND POR

The voltage regulator takes approximately 10

s for it

to generate output. During this time, designated as
T

VREG

, code execution is disabled. T

VREG

is applied

every time the device resumes operation after any
power-down, including Sleep mode. T

VREG

is deter-

mined by the status of the VREGS bit (RCON<8>) and
the WDTWIN Configuration bits (CW3<11:10>). Refer
to

Section 32.0 “Electrical Characteristics”

for more

information on T

VREG

29.2.2

VOLTAGE REGULATOR STANDBY
MODE

The on-chip regulator always consumes a small incre-
mental amount of current over I

, including when

the device is in Sleep mode, even though the core
digital logic does not require power. To provide addi-
tional savings in applications where power resources
are critical, the regulator can be made to enter Standby
mode on its own whenever the device goes into Sleep
mode. This feature is controlled by the VREGS bit
(RCON<8>). Clearing the VREGS bit enables the
Standby mode. When waking up from Standby mode,
the regulator needs to wait for T

VREG

to expire before

wake-up.

29.2.3

LOW-VOLTAGE/RETENTION
REGULATOR

When power-saving modes, such as Sleep and Deep
Sleep are used, PIC24FJ128GA310 family devices
may use a separate low-power, low-voltage/retention
regulator to power critical circuits. This regulator, which
operates at 1.2V nominal, maintains power to data
RAM and the RTCC while all other core digital logic is
powered down. It operates only in Sleep, Deep Sleep
and V

BAT

modes.

The low-voltage/retention regulator is described in more
detail in

Section 10.1.3 “Low-Voltage/Retention

Regulator”

CAP

PIC24FJXXXGA3XX

EFC

3.3V

(1)

Note

This is a typical operating voltage. Refer to