Microchip Technology MA300015 데이터 시트
dsPIC30F6010A/6015
DS70150E-page 122
© 2011 Microchip Technology Inc.
18.3.4
TRANSMIT INTERRUPT
The Transmit Interrupt Flag (U1TXIF or U2TXIF) is
located in the corresponding interrupt flag register.
located in the corresponding interrupt flag register.
The transmitter generates an edge to set the UxTXIF
bit. The condition for generating the interrupt depends
on UTXISEL control bit:
bit. The condition for generating the interrupt depends
on UTXISEL control bit:
a)
If UTXISEL = 0, an interrupt is generated when
a word is transferred from the transmit buffer to
the Transmit Shift Register (UxTSR). This
means that the transmit buffer has at least one
empty word.
a word is transferred from the transmit buffer to
the Transmit Shift Register (UxTSR). This
means that the transmit buffer has at least one
empty word.
b)
If UTXISEL = 1, an interrupt is generated when
a word is transferred from the transmit buffer to
the Transmit Shift Register (UxTSR) and the
transmit buffer is empty.
a word is transferred from the transmit buffer to
the Transmit Shift Register (UxTSR) and the
transmit buffer is empty.
Switching between the two interrupt modes during
operation is possible and sometimes offers more
flexibility.
operation is possible and sometimes offers more
flexibility.
18.3.5
TRANSMIT BREAK
Setting the UTXBRK bit (UxSTA<11>) will cause the
UxTX line to be driven to logic ‘0’. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be Idle
before setting UTXBRK.
UxTX line to be driven to logic ‘0’. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be Idle
before setting UTXBRK.
To send a Break character, the UTXBRK bit must be
set by software and must remain set for a minimum of
13 baud clock cycles. The UTXBRK bit is then cleared
by software to generate Stop bits. The user must wait
for a duration of at least one or two baud clock cycles
in order to ensure a valid Stop bit(s) before reloading
the UxTXB or starting other transmitter activity. Trans-
mission of a Break character does not generate a
transmit interrupt.
set by software and must remain set for a minimum of
13 baud clock cycles. The UTXBRK bit is then cleared
by software to generate Stop bits. The user must wait
for a duration of at least one or two baud clock cycles
in order to ensure a valid Stop bit(s) before reloading
the UxTXB or starting other transmitter activity. Trans-
mission of a Break character does not generate a
transmit interrupt.
18.4
Receiving Data
18.4.1
RECEIVING IN 8-BIT OR 9-BIT DATA
MODE
MODE
The following steps must be performed while receiving
8-bit or 9-bit data:
8-bit or 9-bit data:
1.
2.
A receive interrupt will be generated when one
or more data words have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
or more data words have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
3.
Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
error has occurred. The OERR bit must be reset
in software.
4.
Read the received data from UxRXREG. The act
of reading UxRXREG will move the next word to
the top of the receive FIFO, and the PERR and
FERR values will be updated.
of reading UxRXREG will move the next word to
the top of the receive FIFO, and the PERR and
FERR values will be updated.
18.4.2
RECEIVE BUFFER (U
X
RXB)
The receive buffer is 4 words deep. Including the
Receive Shift Register (UxRSR), the user effectively
has a 5-word deep FIFO buffer.
Receive Shift Register (UxRSR), the user effectively
has a 5-word deep FIFO buffer.
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0 means that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read and no
data shift will occur within the FIFO.
buffer has data available. URXDA = 0 means that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read and no
data shift will occur within the FIFO.
The FIFO is reset during any device Reset. It is not
affected when the device enters or wakes up from a
Power-Saving mode.
affected when the device enters or wakes up from a
Power-Saving mode.
18.4.3
RECEIVE INTERRUPT
The Receive Interrupt Flag (U1RXIF or U2RXIF) can
be read from the corresponding interrupt flag register.
The interrupt flag is set by an edge generated by the
receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
be read from the corresponding interrupt flag register.
The interrupt flag is set by an edge generated by the
receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
a)
If URXISEL<1:0> = 00 or 01, an interrupt is
generated every time a data word is transferred
from the Receive Shift Register (UxRSR) to the
receive buffer. There may be one or more
characters in the receive buffer.
generated every time a data word is transferred
from the Receive Shift Register (UxRSR) to the
receive buffer. There may be one or more
characters in the receive buffer.
b)
If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive
Shift Register (UxRSR) to the receive buffer,
which, as a result of the transfer, contains
3 characters.
when a word is transferred from the Receive
Shift Register (UxRSR) to the receive buffer,
which, as a result of the transfer, contains
3 characters.
c)
If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift
Register (UxRSR) to the receive buffer, which,
as a result of the transfer, contains 4 characters
(i.e., becomes full).
a word is transferred from the Receive Shift
Register (UxRSR) to the receive buffer, which,
as a result of the transfer, contains 4 characters
(i.e., becomes full).
Switching between the interrupt modes during opera-
tion is possible, though generally not advisable during
normal operation.
tion is possible, though generally not advisable during
normal operation.
18.5
Reception Error Handling
18.5.1
RECEIVE BUFFER OVERRUN
ERROR (OERR BIT)
ERROR (OERR BIT)
The OERR bit (UxSTA<1>) is set if all of the following
conditions occur:
conditions occur:
a)
The receive buffer is full.
b)
The Receive Shift Register is full, but unable to
transfer the character to the receive buffer.
transfer the character to the receive buffer.
c)
The Stop bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
Once OERR is set, no further data is shifted in UxRSR
(until the OERR bit is cleared in software or a Reset
occurs). The data held in UxRSR and UxRXREG
remains valid.
(until the OERR bit is cleared in software or a Reset
occurs). The data held in UxRSR and UxRXREG
remains valid.