데이터 시트차례Introduction1Digital PFC and Motor Control1Why Use a Digital Signal Controller?1System Overview2FIGURE 1: Integrated PFC and Sensorless FOC System Block Diagram2A Novel Approach for Digital Implementation of PFC and Sensorless FOC Algorithms3FIGURE 2: Digital PFC and Sensorless FOC Block Diagram3Digital Power Factor Correction4Sensorless Field Oriented Control4Integrated PFC and Sensorless FOC Implementation on a dsPIC DSC Device4FIGURE 3: Timing Diagram5FIGURE 4: State Flow Diagram of Integrated System6FIGURE 5: State Flow Diagram of Digital PFC7FIGURE 6: State Flow Diagram of Sensorless FOC8Implementation on a dsPIC30F6010A Device9ADC Configuration Details9Development Resources9FIGURE 7: ADC Configuration9Hardware Setup10FIGURE 8: Establish common power and digital signal ground10FIGURE 9: Install Feedback Current Selection Resistors11System Execution Procedure11Implementation on a dsPIC33FJ12MC202 Device12ADC Configuration Details12FIGURE 10: ADC Configuration12dsPIC33FJ12MC202 Pin Allocation13TABLE 1: Pin Functionality13Development Resources13Hardware Setup13FIGURE 11: Establish common power and digital signal ground14FIGURE 12: Install Feedback Current Selection Resistors14Interconnecting the Hardware15System Execution Procedure15Laboratory Test Results and Waveforms16FIGURE 13: Input Current and Motor Phase Current Waveforms16FIGURE 14: Expanded Input and Motor Phase Current Waveforms17Conclusion18References18Appendix A: Source Code19크기: 772킬로바이트페이지: 22Language: English매뉴얼 열기
데이터 시트차례1.0 Device Overview9FIGURE 1-1: dsPIC30F6010A Block Diagram10FIGURE 1-2: dsPIC30F6015 Block Diagram11TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (Continued)122.0 CPU Architecture Overview152.1 Core Overview152.2 Programmer’s Model16FIGURE 2-1: dsPIC30F6010A/6015 Programmer’s Model172.3 Divide Support182.4 DSP Engine18TABLE 2-1: DSP Instruction Summary18TABLE 2-2: Divide Instructions18FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM193.0 Memory Organization233.1 Program Address Space23FIGURE 3-1: program Space memory map FOR dsPIC30F6010A/601523TABLE 3-1: Program Space Address Construction24FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION24FIGURE 3-3: Program Data Table Access (least significant word)25FIGURE 3-4: Program Data Table Access (Most Significant Byte)26FIGURE 3-5: Data Space Window Into Program Space Operation273.2 Data Address Space27FIGURE 3-6: dsPIC30F6010A/6015 DATA SPACE MEMORY MAP28FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE29TABLE 3-2: effect of invalid memory accesses30FIGURE 3-8: DATA ALIGNMENT30FIGURE 3-9: CALL Stack FRAME31TABLE 3-3: Core Register Map(1) (Continued)324.0 Address Generator Units354.1 Instruction Addressing Modes35TABLE 4-1: Fundamental Addressing Modes Supported354.2 Modulo Addressing36FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE374.3 Bit-Reversed Addressing38FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE38TABLE 4-2: BiT-Reversed Address Sequence (16-entry)39TABLE 4-3: Bit-Reversed Address Modifier Values For XBREV Register395.0 Interrupts415.1 Interrupt Priority42TABLE 5-1: Interrupt Vector Table425.2 Reset Sequence435.3 Traps43FIGURE 5-1: Trap VECTORS445.4 Interrupt Sequence45FIGURE 5-2: INTERRUPT STACK FRAME455.5 Alternate Vector Table455.6 Fast Context Saving455.7 External Interrupt Requests455.8 Wake-up from Sleep and Idle45TABLE 5-2: Interrupt Controller Register Map For dsPIC30F6010A(1)46TABLE 5-3: Interrupt Controller Register Map For dsPIC30F6015(1)476.0 Flash Program Memory496.1 In-Circuit Serial Programming (ICSP)496.2 Run-Time Self-Programming (RTSP)496.3 Table Instruction Operation Summary49FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS496.4 RTSP Operation506.5 RTSP Control Registers506.6 Programming Operations51EXAMPLE 6-1: erasing A row of PROGRAM memory51EXAMPLE 6-2: loading write latches52EXAMPLE 6-3: initiating a programming sequence52TABLE 6-1: NVM Register Map(1)537.0 Data EEPROM Memory557.1 Reading the Data EEPROM55EXAMPLE 7-1: Data EEPROM Read557.2 Erasing Data EEPROM56EXAMPLE 7-2: Data EEPROM block erase56EXAMPLE 7-3: Data EEPROM Word erase567.3 Writing to the Data EEPROM57EXAMPLE 7-4: Data EEPROM Word Write57EXAMPLE 7-5: data eeprom block write587.4 Write Verify587.5 Protection Against Spurious Write588.0 I/O Ports598.1 Parallel I/O (PIO) Ports59FIGURE 8-1: Block Diagram of a Dedicated PORT Structure59FIGURE 8-2: Block Diagram of a ShAred PORT Structure608.2 Configuring Analog Port Pins60EXAMPLE 8-1: Port Write/Read Example60TABLE 8-1: dsPIC30F6010A PORT Register MAp(1)61TABLE 8-2: dsPIC30F6015 PORT Register MAp(1)628.3 Input Change Notification Module63TABLE 8-3: Input change notification register map (Bits 15-8)(1)63TABLE 8-4: Input Change notification register map (Bits 7-0) for dsPIC30F6010A(1)63TABLE 8-5: Input Change notification register map (Bits 7-0) for dsPIC30F6015(1)639.0 Timer1 Module65FIGURE 9-1: 16-bit Timer1 Module Block diagram (Type A Timer)659.1 Timer Gate Operation669.2 Timer Prescaler669.3 Timer Operation During Sleep Mode669.4 Timer Interrupt669.5 Real-Time Clock66FIGURE 9-2: Recommended Components for Timer1 LP Oscillator RTC66TABLE 9-1: Timer1 Register Map(1)6810.0 Timer2/3 Module69FIGURE 10-1: 32-bit TIMER2/3 BLOCK DIAGRAM fOR DSPic30f6010a70FIGURE 10-2: 32-bit TIMER2/3 BLOCK DIAGRAM fOR DSPic30f601571FIGURE 10-3: 16-bit TIMER2 BLOCK DIAGRAM (Type B Timer) fOR DSpic30f6010a72FIGURE 10-4: 16-bit TIMER2 BLOCK DIAGRAM (Type B Timer) fOR DSpic30f601572FIGURE 10-5: 16-bit TIMER3 BLOCK DIAGRAM (Type C Timer)7310.1 Timer Gate Operation7410.2 ADC Event Trigger7410.3 Timer Prescaler7410.4 Timer Operation During Sleep Mode7410.5 Timer Interrupt74TABLE 10-1: Timer2/3 register map(1)7511.0 Timer4/5 Module77FIGURE 11-1: 32-bit TIMER4/5 BLOCK DIAGRAM77FIGURE 11-2: 16-bit TIMER4 BLOCK DIAGRAM (Type B Timer)78FIGURE 11-3: 16-bit TIMER5 BLOCK DIAGRAM (Type C Timer)78TABLE 11-1: Timer4/5 register map(1)7912.0 Input Capture Module8112.1 Simple Capture Event Mode81FIGURE 12-1: Input Capture Mode Block Diagram8112.2 Input Capture Operation During Sleep and Idle Modes8212.3 Input Capture Interrupts82TABLE 12-1: Input Capture Register Map(1)8313.0 Output Compare Module85FIGURE 13-1: Output Compare Mode Block DiagrAm8513.1 Timer2 and Timer3 Selection Mode8613.2 Simple Output Compare Match Mode8613.3 Dual Output Compare Match Mode8613.4 Simple PWM Mode86EQUATION 13-1: PWM Period87FIGURE 13-2: PWM output Timing8713.5 Output Compare Operation During CPU Sleep Mode8813.6 Output Compare Operation During CPU Idle Mode8813.7 Output Compare Interrupts88TABLE 13-1: Output Compare Register Map(1)8914.0 Quadrature Encoder Interface (QEI) Module91FIGURE 14-1: Quadrature Encoder Interface Block Diagram9114.1 Quadrature Encoder Interface Logic9214.2 16-bit Up/Down Position Counter Mode9214.3 Position Measurement Mode9214.4 Programmable Digital Noise Filters9314.5 Alternate 16-bit Timer/Counter9314.6 QEI Module Operation During CPU Sleep Mode9314.7 QEI Module Operation During CPU Idle Mode9314.8 Quadrature Encoder Interface Interrupts94TABLE 14-1: QEI register map(1)9515.0 Motor Control PWM Module97FIGURE 15-1: PWM module Block Diagram9815.1 PWM Time Base9915.2 PWM Period100EQUATION 15-1: PWM Period100EQUATION 15-2: PWM Period for Up/ Down Count100EQUATION 15-3: PWM Resolution10015.3 Edge-Aligned PWM100FIGURE 15-2: Edge-Aligned PWM10015.4 Center-Aligned PWM101FIGURE 15-3: Center-aligned PwM10115.5 PWM Duty Cycle Comparison Units10115.6 Complementary PWM Operation10215.7 Dead-Time Generators102TABLE 15-1: Dead-Time selection bits102FIGURE 15-4: Dead-time TIMING diagram10315.8 Independent PWM Output10315.9 Single-Pulse PWM Operation10315.10 PWM Output Override10315.11 PWM Output and Polarity Control10415.12 PWM Fault Pins10415.13 PWM Update Lockout10515.14 PWM Special Event Trigger10515.15 PWM Operation During CPU Sleep Mode10515.16 PWM Operation During CPU Idle Mode105TABLE 15-2: 8-output PWM Register Map(1)10616.0 SPI Module10716.1 Operating Function Description107FIGURE 16-1: SPI BLOCK DIAGRAM108FIGURE 16-2: SPI Master/Slave Connection10816.2 Framed SPI Support10916.3 Slave Select Synchronization10916.4 SPI Operation During CPU Sleep Mode10916.5 SPI Operation During CPU Idle Mode109TABLE 16-1: SPI1 Register Map(1)110TABLE 16-2: SPI2 Register Map(1)11017.0 I2C™ Module11117.1 Operating Function Description111FIGURE 17-1: Programmer’s model111FIGURE 17-2: I2C™ BLOCK DIAGRAM11217.2 I2C Module Addresses113TABLE 17-1: 7-bit I2C™ Slave Addresses supported by dsPIC30F11317.3 I2C 7-bit Slave Mode Operation11317.4 I2C 10-bit Slave Mode Operation11317.5 Automatic Clock Stretch11417.6 Software Controlled Clock Stretching (STREN = 1)11417.7 Interrupts11517.8 Slope Control11517.9 IPMI Support11517.10 General Call Address Support11517.11 I2C Master Support11517.12 I2C Master Operation11517.13 I2C Module Operation During CPU Sleep and Idle Modes116TABLE 17-2: I2C™ Register Map(1)11718.0 Universal Asynchronous Receiver Transmitter (UART) Module11918.1 UART Module Overview119FIGURE 18-1: UART Transmitter Block Diagram119FIGURE 18-2: UART Receiver Block Diagram12018.2 Enabling and Setting Up UART12118.3 Transmitting Data12118.4 Receiving Data12218.5 Reception Error Handling12218.6 Address Detect Mode12318.7 Loopback Mode12318.8 Baud Rate Generator (BRG)123EQUATION 18-1: Baud Rate12318.9 Auto-Baud Support12418.10 UART Operation During CPU Sleep and Idle Modes124TABLE 18-1: UART1 Register Map(1)125TABLE 18-2: UART2 Register Map(1)12519.0 CAN Module12719.1 Overview12719.2 Frame Types127FIGURE 19-1: CAN Buffers and Protocol Engine Block Diagram12819.3 Modes of Operation12919.4 Message Reception13019.5 Message Transmission13119.6 Baud Rate Setting132FIGURE 19-2: CAN Bit Timing132EQUATION 19-1: Time Quantum For Clock Generation133TABLE 19-1: CAN1 Register Map for dsPIC30F6010A and 6015 Devices(1) (Continued)134TABLE 19-2: CAN2 Register Map for dsPIC30F6010A(1) (Continued)13620.0 10-bit High-Speed Analog- to-Digital Converter (ADC) Module139FIGURE 20-1: 10-bit High-Speed A/D Functional Block Diagram14020.1 A/D Result Buffer14120.2 Conversion Operation14120.3 Selecting the Conversion Sequence14120.4 Programming the Start of Conversion Trigger14220.5 Aborting a Conversion14220.6 Selecting the A/D Conversion Clock142EQUATION 20-1: A/D CONVERSION CLOCK142EXAMPLE 20-1: A/D Conversion Clock Calculation14220.7 A/D Conversion Speeds143TABLE 20-1: 10-bit A/D Conversion Rate Parameters143FIGURE 20-2: A/D converter Voltage Reference Schematic14420.8 A/D Acquisition Requirements146FIGURE 20-3: A/D Converter Analog Input Model14620.9 Module Power-Down Modes14720.10 A/D Operation During CPU Sleep and Idle Modes14720.11 Effects of a Reset14720.12 Output Formats147FIGURE 20-4: A/D output data formats14720.13 Configuring Analog Port Pins14820.14 Connection Considerations148TABLE 20-2: ADC Register Map(1)14921.0 System Integration15121.1 Oscillator System Overview151TABLE 21-1: Oscillator Operating Modes152FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM15321.2 Oscillator Configurations154TABLE 21-2: .Configuration Bit Values for Clock Selection154TABLE 21-3: PLL frequency range155TABLE 21-4: FRC Tuning15521.3 Reset157FIGURE 21-2: Reset SYSTEM BLOCK DIAGRAM157FIGURE 21-3: Time-out Sequence on Power-up (MCLR Tied to Vdd)158FIGURE 21-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1158FIGURE 21-5: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2158FIGURE 21-6: External Power-on Reset Circuit (for Slow Vdd Power-up)159TABLE 21-5: Initialization Condition for RCON RegisteR CASE 1160TABLE 21-6: Initialization Condition for RCON RegisteR CASE 216021.4 Watchdog Timer (WDT)16121.5 Power-Saving Modes16121.6 Device Configuration Registers16221.7 Peripheral Module Disable (PMD) Registers16321.8 In-Circuit Debugger163TABLE 21-7: System Integration Register Map for dsPIC30F6010A Devices(1)164TABLE 21-8: System Integration Register Map for dsPIC30F6015 Devices(1)164TABLE 21-9: DEVICE Configuration Register Map(1)16422.0 Instruction Set Summary165TABLE 22-1: Symbols used in Opcode Descriptions (Continued)166TABLE 22-2: Instruction Set OVERVIEW (Continued)16823.0 Development Support17324.0 Electrical Characteristics17724.1 DC Characteristics178TABLE 24-1: Operating MIPS vs. Voltage for dsPIC30F6010A178TABLE 24-2: Operating MIPS vs. Voltage for dsPIC30F6015178TABLE 24-3: Thermal Operating Conditions178TABLE 24-4: Thermal Packaging Characteristics178TABLE 24-5: DC Temperature and Voltage specifications179TABLE 24-6: DC Characteristics: Operating Current (Idd)180TABLE 24-7: DC Characteristics: Idle Current (iidle)181TABLE 24-8: DC Characteristics: Power-Down Current (Ipd)182TABLE 24-9: DC Characteristics: I/O Pin Input Specifications183TABLE 24-10: DC Characteristics: I/O Pin Output Specifications184FIGURE 24-1: Brown-out Reset Characteristics184TABLE 24-11: Electrical Characteristics: BOR185TABLE 24-12: DC Characteristics: Program and EEPROM18524.2 AC Characteristics and Timing Parameters186TABLE 24-13: Temperature and Voltage Specifications – AC186FIGURE 24-2: Load Conditions for Device Timing Specifications186FIGURE 24-3: External Clock Timing186TABLE 24-14: External Clock Timing Requirements187TABLE 24-15: PLL Clock Timing Specifications (Vdd = 2.5 to 5.5 V)188TABLE 24-16: PLL Jitter188TABLE 24-17: Internal Clock Timing examples189TABLE 24-18: AC Characteristics: Internal FRC Accuracy190TABLE 24-19: AC Characteristics: Internal LPRC accuracy190FIGURE 24-4: CLKOUT and I/O Timing Characteristics191TABLE 24-20: CLKOUT and I/O Timing Requirements191FIGURE 24-5: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics192TABLE 24-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Timing Requirements193FIGURE 24-6: band gap Start-up Time Characteristics193TABLE 24-22: band gap Start-up Time Requirements193FIGURE 24-7: Timer1, 2, 3, 4 and 5 External Clock Timing Characteristics194TABLE 24-23: Timer1 External Clock Timing Requirements194TABLE 24-24: Timer2 and Timer4 External Clock Timing Requirements195TABLE 24-25: Timer3 and Timer5 External Clock Timing Requirements195FIGURE 24-8: TimerQ (QEI Module) External Clock Timing Characteristics196TABLE 24-26: QEI module External Clock Timing Requirements196FIGURE 24-9: INPUT CAPTURE (CAPx) TIMING Characteristics197TABLE 24-27: Input Capture timing requirements197FIGURE 24-10: Output Compare Module (OCx) Timing Characteristics197TABLE 24-28: Output Compare Module timing requirements197FIGURE 24-11: OC/PWM Module Timing Characteristics198TABLE 24-29: Simple OC/PWM MODE Timing Requirements198FIGURE 24-12: Motor Control PWM Module fault Timing Characteristics199FIGURE 24-13: Motor Control PWM Module Timing Characteristics199TABLE 24-30: Motor Control PWM Module Timing Requirements199FIGURE 24-14: QEA/QEB Input Characteristics200TABLE 24-31: Quadrature Decoder Timing Requirements200FIGURE 24-15: QEI Module Index Pulse Timing Characteristics201TABLE 24-32: QEI INDEX PULSE Timing Requirements201FIGURE 24-16: SPI Module Master Mode (CKE = 0) Timing Characteristics202TABLE 24-33: SPI Master mode (cke = 0) Timing requirements202FIGURE 24-17: SPI Module Master Mode (CKE =1) Timing Characteristics203TABLE 24-34: SPI Module Master mode (cke = 1) Timing requirements203FIGURE 24-18: SPI Module Slave Mode (CKE = 0) Timing Characteristics204TABLE 24-35: SPI Module Slave mode (cke = 0) Timing requirements204FIGURE 24-19: SPI Module Slave Mode (CKE = 1) Timing Characteristics205TABLE 24-36: SPI Module Slave mode (cke = 1) Timing requirements206FIGURE 24-20: I2C™ Bus Start/Stop Bits Timing Characteristics (Master mode)207FIGURE 24-21: I2C™ Bus Data Timing Characteristics (Master mode)207TABLE 24-37: I2C™ Bus Data Timing Requirements (Master Mode)208FIGURE 24-22: I2C™ Bus Start/Stop Bits Timing Characteristics (slave mode)209FIGURE 24-23: I2C™ Bus Data Timing Characteristics (slave mode)209TABLE 24-38: I2C™ Bus Data Timing Requirements (Slave Mode210FIGURE 24-24: CAN Module I/O Timing Characteristics211TABLE 24-39: CAN Module I/O Timing Requirements211TABLE 24-40: 10-bit High-speed a/d Module Specifications(1) (Continued)212FIGURE 24-25: 10-Bit High-speed A/D Conversion Timing Characteristics (chps = 01, SIMSAM = 0, asam = 0, ssrc = 000)214FIGURE 24-26: 10-Bit High-speed A/D Conversion Timing cHARACTERISTICS (chps = 01, SIMSAM = 0, asam = 1, ssrc = 111, SAMC = 00001)215TABLE 24-41: 10-Bit HIGH-SPEED A/D CONVERSION TIMING rEQUIREMENTS21625.0 Packaging Information21725.1 Package Marking Information217Appendix A: Revision History225TABLE A-1: Major Section Updates226INDEX227크기: 3.31메가바이트페이지: 236Language: English매뉴얼 열기
