Microchip Technology MA300015 데이터 시트

© 2011 Microchip Technology Inc.

DS70150E-page 93

The digital noise filter section is responsible for
rejecting noise on the incoming quadrature signals.
Schmitt Trigger inputs and a three-clock cycle delay
filter combine to reject low level noise and large, short
duration noise spikes that typically occur in noise prone
applications, such as a motor system.

The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.

For the QEA, QEB and INDX pins, the clock divide
frequency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from
the base instruction cycle T

CY

.

To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR and BOR. 

When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
as a simple 16-bit timer/counter. The setup and control
of the auxiliary timer is accomplished through the QEI-
CON SFR register. This timer functions identically to
Timer1. The QEA pin is used as the timer clock input.

When configured as a timer, the POSCNT register
serves as the Timer Count register and the MAXCNT
register serves as the Period register. When a Timer/
Period register match occur, the QEI interrupt flag will
be asserted.

The only exception between the general purpose
timers and this timer is the added feature of external
up/down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.

The UPDN control/Status bit (QEICON<11>) can be
used to select the count direction state of the Timer
register. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.

In addition, control bit, UDSRC (QEICON<0>), deter-
mines whether the timer count direction state is based
on the logic state, written into the UPDN control/Status
bit (QEICON<11>), or the QEB pin state. When
UDSRC = 1, the timer count direction is controlled from
the QEB pin. Likewise, when UDSRC = 0, the timer
count direction is controlled by the UPDN bit.

14.6.1

QEI OPERATION DURING CPU 
SLEEP MODE

The QEI module will be halted during the CPU Sleep
mode.

14.6.2

TIMER OPERATION DURING CPU 
SLEEP MODE

During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.

Since the QEI module can function as a Quadrature
Encoder Interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.

14.7.1

QEI OPERATION DURING CPU IDLE 
MODE

When the CPU is placed in the Idle mode, the QEI
module will operate if the QEISIDL bit (QEICON<13>)
= 0. This bit defaults to a logic ‘0’ upon executing POR
and BOR. For halting the QEI module during the CPU
Idle mode, QEISIDL should be set to ‘1’.

Changing the operational mode (i.e., from
QEI to Timer or vice versa), will not affect
the Timer/Position Count register contents.

This Timer does not support the External
Asynchronous Counter mode of operation.
If using an external clock source, the clock
will automatically be synchronized to the
internal instruction cycle.