Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MPL3115A2
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
25
7.4
Time Delay Register
7.4.1
TIME_DLY(0x10)
The time delay register contains the number of ticks of data sample time since the last byte of the FIFO was written.
This register starts to increment on FIFO overflow or data wrap and clears when last byte of FIFO is read.
This register starts to increment on FIFO overflow or data wrap and clears when last byte of FIFO is read.
7.5
System Mode Register
7.5.1
SYSMOD (0x11)
The system mode register indicates the current device operating mode.
7.6
System Interrupt Status
7.6.1
INT_SOURCE (0x12)
Interrupt source register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits
that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
The setting of the bits is rising edge sensitive, the bit is set by a low to high state change and reset by reading the appropriate
source register.
F_WMRK[5:0]
(2)
FIFO Event Sample Count Watermark.
Default value: 00_0000.
These bits set the number of FIFO samples required to trigger a watermark interrupt. A FIFO watermark event flag
(F_WMRK_FLAG) is raised when FIFO sample count F_CNT[5:0] value is equal to the F_ WMRK[5:0] watermark.
Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.
Default value: 00_0000.
These bits set the number of FIFO samples required to trigger a watermark interrupt. A FIFO watermark event flag
(F_WMRK_FLAG) is raised when FIFO sample count F_CNT[5:0] value is equal to the F_ WMRK[5:0] watermark.
Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.
1. This bit field can be written in ACTIVE mode.
2. This bit field can be written in STANDBY mode.
3. The FIFO mode (F_MODE) cannot be switched between the two operational modes (01 & 10).
2. This bit field can be written in STANDBY mode.
3. The FIFO mode (F_MODE) cannot be switched between the two operational modes (01 & 10).
Table 32. Time Delay Register
7
6
5
4
3
2
1
0
R
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
W
Reset
0
0
0
0
0
0
0
0
Table 33. SYSMOD Register
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
SYSMOD
W
Reset
0
0
0
0
0
0
0
0
Table 34. SYSMOD Bit Descriptions
Name
Description
RESERVED
Reserved Bits 7-1, will always read 0.
SYSMOD
System mode. Default value: 0.
0: STANDBY mode
1: ACTIVE mode
0: STANDBY mode
1: ACTIVE mode
Table 35. INT_SOURCE Register
7
6
5
4
3
2
1
0
R
SRC_DRDY
SRC_FIFO
SRC_PW
SRC_TW
SRC_PTH
SRC_TTH
SRC_PCHG
SRC_TCHG
W
Reset
0
0
0
0
0
0
0
0
Table 31. F_SETUP Bit Descriptions