Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MMA8652FC
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
17
5.10
Interrupt register configurations
There are seven configurable interrupts in the MMA8652FC: Data Ready, Motion/Freefall, Tap (Pulse), Orientation, Transient,
FIFO events, and Auto-SLEEP events.
FIFO events, and Auto-SLEEP events.
Figure 9. System interrupt generation
•
The MMA8652FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus
simplifying data synchronization in the digital system that uses the device.
simplifying data synchronization in the digital system that uses the device.
•
The MMA8652FC may also be configured to generate other interrupt signals accordingly, to the programmable embedded
functions of the device for Motion, Freefall, Transient, Orientation, and Tap.
functions of the device for Motion, Freefall, Transient, Orientation, and Tap.
5.11
Serial I
2
C interface
Acceleration data may be accessed through an I
2
C interface, thus making the device particularly suitable for direct interfacing to
a microcontroller. The acceleration data and configuration registers embedded inside the MMA8652FC are accessed through the
I
I
2
C serial interface (
Table 10
).
•
To enable the I
2
C interface, VDDIO line must be tied high (to the interface supply voltage). If VDD is not present and VDDIO
is present, then the MMA8652FC is in OFF mode—and communications on the I
2
C interface are ignored.
•
The I
2
C interface may be used for communications between other I
2
C devices; the MMA8652FC does not affect the I
2
C bus.
The I
2
C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I
2
C standards (
Table 11
).
I
2
C operation:
1.
The transaction on the bus is started through a start condition (START) signal. A START condition is defined as a high-to-
low transition on the data line while the SCL line is held high. After START has been transmitted by the Master, the bus is
considered busy.
low transition on the data line while the SCL line is held high. After START has been transmitted by the Master, the bus is
considered busy.
2.
The next byte of data transmitted after START contains the slave address in the first seven bits. The eighth bit tells
whether the Master is receiving data from the slave or is transmitting data to the slave.
whether the Master is receiving data from the slave or is transmitting data to the slave.
3.
After a start condition and when an address is sent, each device in the system compares the first seven bits with its
address. If the device’s address matches the sent address, then the device considers itself addressed by the Master.
address. If the device’s address matches the sent address, then the device considers itself addressed by the Master.
Table 10. Serial Interface pins
Pin Name
Pin Description
Notes
SCL
I
2
C Serial Clock
There are two signals associated with the I
2
C bus; the Serial Clock Line (SCL) and the
Serial Data line (SDA).
• SDA is a bidirectional line used for sending and receiving the data to/from the interface.
• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus
• SDA is a bidirectional line used for sending and receiving the data to/from the interface.
• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus
is free, both SCL and SDA lines are high.
SDA
I
2
C Serial Data
Interrupt
Controller
Data Ready
Motion/Freefall
Tap (Pulse)
Orientation
Transient
FIFO
Auto-SLEEP
INT ENABLE
INT CFG
INT1
INT2
7
7
Configurable interrupts
These seven interrupt sources can be
routed to one of two interrupt pins.
routed to one of two interrupt pins.
The interrupt source must be enabled
and configured.
and configured.
If the event flag is asserted because
the event condition is detected, then
the corresponding interrupt pin (INT1
or INT2) will assert.
the event condition is detected, then
the corresponding interrupt pin (INT1
or INT2) will assert.