Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MMA8652FC
Sensors
18
Freescale Semiconductor, Inc.
4.
The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The
transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it
remains stable low during the high period of the acknowledge clock period.
transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it
remains stable low during the high period of the acknowledge clock period.
5.
A Master may also issue a repeated START during a data transfer. The MMA8652FC expects repeated STARTs to be
used to randomly read from specific registers.
used to randomly read from specific registers.
6.
A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer
is always terminated by a STOP.
is always terminated by a STOP.
The MMA8652FC's standard slave address is 0011101 or 0x01D. The slave addresses are factory programmed; alternate
addresses are available upon request.
addresses are available upon request.
5.11.1
Single-byte read
1.
The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send
the command, note that the data returned is sent with the MSB first after the data is received.
the command, note that the data returned is sent with the MSB first after the data is received.
Figure 10
shows the
timing diagram for the accelerometer 8-bit I
2
C read operation.
2.
The Master (or MCU) transmits a start condition (ST) to the MMA8652FC [slave address (0x1D), with the R/W bit set to
“0” for a write], and the MMA8652FC sends an acknowledgement.
“0” for a write], and the MMA8652FC sends an acknowledgement.
3.
Next the Master (or MCU) transmits the address of the register to read, and the MMA8652FC sends an
acknowledgement.
acknowledgement.
4.
The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8652FC (0x1D), with the
R/W bit set to “1” for a read from the previously selected register.
R/W bit set to “1” for a read from the previously selected register.
5.
The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge
(NAK) the transmitted data, but transmits a stop condition to end the data transfer.
(NAK) the transmitted data, but transmits a stop condition to end the data transfer.
Figure 10. Single-Byte Read timing (I
2
C)
NOTE
For the following subsections, use the following legend.
5.11.2
Multiple byte read
(See
Table 11
for next auto-increment address.)
1.
When performing a multi-byte read or “burst read”, the MMA8652FC automatically increments the received register
address commands after a read command is received.
address commands after a read command is received.
2.
After following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each
MMA8652FC acknowledgment (AK) is received,
MMA8652FC acknowledgment (AK) is received,
3.
Until a no acknowledge (NAK) occurs from the Master,
4.
Followed by a stop condition (SP), which signals the end of transmission.
Table 11. I
2
C Device address sequence
Command
[6:0]
Device address
[6:0]
Device address
R/W
8-bit final
value
Read
0011101
0x1D
1
0x3B
Write
0011101
0x1D
0
0x3A
Master
ST Device Address[7:1]
W
Register
Address[7:0]
SR Device Address[7:1]
R
NAK
SP
Slave
AK
AK
AK
Data[7:0]
Legend
ST: Start Condition
SP: Stop Condition
NAK: No Acknowledge
W: Write = 0
SR: Repeated Start Condition
AK: Acknowledge
R: Read = 1