Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MMA8652FC
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
33
6.7.2
0x11 Portrait/Landscape Configuration register
The Portrait/Landscape Configuration register enables the portrait/landscape function and sets the behavior of the debounce
counter.
counter.
6.7.3
0x12 Portrait/Landscape Debounce register
The Portrait/Landscape Debounce register sets the debounce count for the orientation state transition. The minimum debounce
latency is determined by the data rate (which is set by the product of the selected system ODR and PL_COUNT registers). Any
transition from WAKE to SLEEP (or SLEEP to Wake) resets the internal Landscape/Portrait debounce counter.
latency is determined by the data rate (which is set by the product of the selected system ODR and PL_COUNT registers). Any
transition from WAKE to SLEEP (or SLEEP to Wake) resets the internal Landscape/Portrait debounce counter.
NOTE
The debounce counter weighting (time step) changes, based on the ODR and the
Oversampling mode.
Oversampling mode.
Table 40
explains the time step value for all sample rates and all
Oversampling modes.
Table 36. 0x11 PL_CFG register (Read/Write)
Back to Register Address Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBCNTM
PL_EN
—
—
—
—
—
—
Table 37. PL_CFG register
Bit(s)
Field
Description
7
DBCNTM
Debounce counter mode selection
0 Decrements debounce whenever the condition of interest is no longer valid.
1 Clears the counter whenever the condition of interest is no longer valid. (default)
0 Decrements debounce whenever the condition of interest is no longer valid.
1 Clears the counter whenever the condition of interest is no longer valid. (default)
6
PL_EN
Portrait/Landscape detection enable
0 Portrait/Landscape Detection is disabled. (default)
1 Portrait/Landscape Detection is enabled.
0 Portrait/Landscape Detection is disabled. (default)
1 Portrait/Landscape Detection is enabled.
5–0
—
Can be 0 or 1.
Table 38. 0x12 PL_COUNT register (Read/Write)
Back to Register Address Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBNCE[7]
DBNCE[6]
DBNCE[5]
DBNCE[4]
DBNCE[3]
DBNCE[2]
DBNCE[1]
DBNCE[0]
Table 39. PL_COUNT register
Bit(s)
Field
Description
7–0
DBCNE[7:0]
Debounce Count value
0000_0000 (default)
0000_0000 (default)
Table 40. PL_COUNT relationship with the ODR
ODR
(Hz)
Max Time Range (s)
Time Step (ms)
Normal
LPLN
HighRes
LP
Normal
LPLN
HighRes
LP
800
0.319
0.319
0.319
0.319
1.25
1.25
1.25
1.25
400
0.638
0.638
0.638
0.638
2.5
2.5
2.5
2.5
200
1.28
1.28
0.638
1.28
5
5
2.5
5
100
2.55
2.55
0.638
2.55
10
10
2.5
10
50
5.1
5.1
0.638
5.1
20
20
2.5
20
12.5
5.1
20.4
0.638
20.4
20
80
2.5
80
6.25
5.1
20.4
0.638
40.8
20
80
2.5
160
1.56
5.1
20.4
0.638
40.8
20
80
2.5
160