Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MMA8652FC
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
55
6.12.3
0x2C: CTRL_REG3 Interrupt Control register
CTRL_REG3 register is used to control the Auto-WAKE/SLEEP function by setting the orientation or Freefall/Motion as an
interrupt to wake. CTRL_REG3 register also configures the interrupt pins INT1 and INT2.
interrupt to wake. CTRL_REG3 register also configures the interrupt pins INT1 and INT2.
Table 101. MODS Oversampling modes averaging values at each ODR
ODR
(Hz)
Mode
Normal (00)
Low Noise Low Power (01)
High Resolution (10)
Low Power (11)
Current
A
OS Ratio
Current
A
OS Ratio
Current
A
OS Ratio
Current
A
OS Ratio
1.56
27
128
9
32
184
1024
6.5
16
6.25
27
32
9
8
184
256
6.5
4
12.5
27
16
9
4
184
128
6.5
2
50
27
4
27
4
184
32
15
2
100
49
4
49
4
184
16
26
2
200
94
4
94
4
184
8
49
2
400
184
4
184
4
184
4
94
2
800
184
2
184
2
184
2
184
2
Table 102. 0x2C CTRL_REG3 register (Read/Write)
Back to Register Address Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIFO_GATE
WAKE_TRANS
WAKE_LNDPRT
WAKE_PULSE
WAKE_FF_MT
0
IPOL
PP_OD
Table 103. CTRL_REG3 register
Bit(s)
Field
Description
7
FIFO_GATE
FIFO Gate
0 FIFO gate is bypassed. (default)
0 FIFO gate is bypassed. (default)
FIFO is flushed upon the system mode transitioning from WAKE to SLEEP mode or from SLEEP to WAKE
mode.
mode.
1 The FIFO input buffer is blocked when transitioning from WAKE to SLEEP mode or from SLEEP to WAKE
mode, until the FIFO is flushed. Although the system transitions from WAKE to SLEEP or from SLEEP to
WAKE—the contents of the FIFO buffer are preserved, and new data samples are ignored until the FIFO is
emptied by the host application.
If the FIFO_GATE bit is set to 1 and the FIFO buffer is not emptied before the arrival of the next sample,
then the FGERR bit in the SYS_MOD register (0x0B) will be asserted. The FGERR bit remains asserted as
long as the FIFO buffer remains un-emptied. Emptying the FIFO buffer clears the FGERR bit in the
SYS_MOD register.
WAKE—the contents of the FIFO buffer are preserved, and new data samples are ignored until the FIFO is
emptied by the host application.
If the FIFO_GATE bit is set to 1 and the FIFO buffer is not emptied before the arrival of the next sample,
then the FGERR bit in the SYS_MOD register (0x0B) will be asserted. The FGERR bit remains asserted as
long as the FIFO buffer remains un-emptied. Emptying the FIFO buffer clears the FGERR bit in the
SYS_MOD register.
6
WAKE_TRANS
Wake from Transient interrupt
0 Transient function is bypassed in SLEEP mode. (default)
1 Transient function interrupt can wake up system
0 Transient function is bypassed in SLEEP mode. (default)
1 Transient function interrupt can wake up system
5
WAKE_LNDPRT
Wake from Orientation interrupt
0 Orientation function is bypassed in SLEEP mode. (default)
1 Orientation function interrupt can wake up system
0 Orientation function is bypassed in SLEEP mode. (default)
1 Orientation function interrupt can wake up system
4
WAKE_PULSE
Wake from Pulse interrupt
0 Pulse function is bypassed in SLEEP mode. (default)
1 Pulse function interrupt can wake up system
0 Pulse function is bypassed in SLEEP mode. (default)
1 Pulse function interrupt can wake up system
3
WAKE_FF_MT
Wake from Freefall/Motion interrupt
0 Freefall/Motion function is bypassed in SLEEP mode. (default)
1 Freefall/Motion function interrupt can wake up
0 Freefall/Motion function is bypassed in SLEEP mode. (default)
1 Freefall/Motion function interrupt can wake up
2
0
1
IPOL
Interrupt polarity
Selects the polarity of the interrupt signals.
When IPOL is 0 (default value), any interrupt event is signaled with a logical 0.
0 ACTIVE low (default)
1 ACTIVE high
Selects the polarity of the interrupt signals.
When IPOL is 0 (default value), any interrupt event is signaled with a logical 0.
0 ACTIVE low (default)
1 ACTIVE high